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Baremetal Framework with personalized A2B configuration issue

Category: Software
Product Number: ADZS-SC589-MINI
Software Version: Cross Core Embedded Studio 2.9.3

Hi everyone,

I'm using the baremetal framework https://wiki.analog.com/resources/tools-software/sharc-audio-module/baremetal in CCES 2.9.3 to create a project using the A2B. In particular, I'm trying to use the AD2428W transceiver on the ADZS-SC589-MINI as A2B master and the AD2428W transceiver on the EVAL-AD2428WC1BZ. I would like to listen the audio channels from mics (the four PDM microphones on EVAL-AD2428WC1BZ) in my headphones. 

To set the A2B configuration I used SigmaStudio 4.5 creating the following diagram.

Here I attach also the exported .h file from this diagram.

/*******************************************************************************
Copyright (c) 2022 - Analog Devices Inc. All Rights Reserved.
This software is proprietary & confidential to Analog Devices, Inc.
and its licensors.
******************************************************************************
* @brief: This file contains I2C command sequence to be followed for discovery 
*         and configuration of A2B nodes for an A2B schematic
* @version: $Revision$
* @date: Tuesday, October 4, 2022-10:56:04 AM
* I2C Command File Version - 1.0.0
* A2B DLL version- 19.3.0
* A2B Stack DLL version- 19.3.0.0
* SigmaStudio version- 4.05.000.1779
* Developed by: Automotive Software and Systems team, Bangalore, India
* THIS IS A SIGMASTUDIO GENERATED FILE
*****************************************************************************/

/*! \addtogroup ADI_A2B_DISCOVERY_CONFIG ADI_A2B_DISCOVERY_CONFIG 
* @{
*/
#ifndef _ADI_A2B_I2C_LIST_H_ 
#define _ADI_A2B_I2C_LIST_H_ 

/*! \struct ADI_A2B_DISCOVERY_CONFIG 
A2B discovery config unit structure 
*/
typedef struct 
 { 
/*!  Device address */
	unsigned char nDeviceAddr;

/*!  Operation code */
	unsigned char eOpCode;

/*! Reg Sub address width (in bytes) */
	unsigned char nAddrWidth;

/*! Reg Sub address */
	unsigned int nAddr;

/*! Reg data width (in bytes) */
	unsigned char nDataWidth;

/*! Reg data count (in bytes) */
	unsigned short nDataCount;

/*! Config Data */
	unsigned char* paConfigData;


} ADI_A2B_DISCOVERY_CONFIG;

#define WRITE   ((unsigned char) 0x00u)
#define READ    ((unsigned char) 0x01u)
#define DELAY   ((unsigned char) 0x02u)
#define INVALID ((unsigned char) 0xffu)

#define CONFIG_LEN (112) 


static unsigned char gaConfig_master_CONTROL_Data0[1] =
{
	0x84u	
};

static unsigned char gaConfig_master_A2BDelay_Data1[1] =
{
	0x19u	
};

static unsigned char gaConfig_master_INTTYPE_Data2[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_INTMSK0_Data3[1] =
{
	0x77u	
};

static unsigned char gaConfig_master_INTMSK1_Data4[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_INTMSK2_Data5[1] =
{
	0x0Fu	
};

static unsigned char gaConfig_master_RESPCYCS_Data6[1] =
{
	0x6Bu	
};

static unsigned char gaConfig_master_CONTROL_Data7[1] =
{
	0x01u	
};

static unsigned char gaConfig_master_I2SGCFG_Data8[1] =
{
	0x80u	
};

static unsigned char gaConfig_master_SWCTL_Data9[1] =
{
	0x01u	
};

static unsigned char gaConfig_master_DISCVRY_Data10[1] =
{
	0x6Bu	
};

static unsigned char gaConfig_master_A2BDelay_Data11[1] =
{
	0x32u	
};

static unsigned char gaConfig_master_INTPND2_Data12[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_INTPND2_Data13[1] =
{
	0x01u	
};

static unsigned char gaConfig_master_NODEADR_Data14[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_VENDOR_Data0[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_PRODUCT_Data1[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_VERSION_Data2[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_SWCTL_Data15[1] =
{
	0x21u	
};

static unsigned char gaConfig_master_NODEADR_Data16[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_BCDNSLOTS_Data3[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_LDNSLOTS_Data4[1] =
{
	0x80u	
};

static unsigned char gaConfig_slave1_LUPSLOTS_Data5[1] =
{
	0x04u	
};

static unsigned char gaConfig_slave1_I2CCFG_Data6[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_SYNCOFFSET_Data7[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_I2SGCFG_Data8[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_I2SCFG_Data9[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_I2SRATE_Data10[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_PDMCTL_Data11[1] =
{
	0x1Fu	
};

static unsigned char gaConfig_slave1_PDMCTL2_Data12[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_ERRMGMT_Data13[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_GPIODAT_Data14[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_GPIOOEN_Data15[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_GPIOIEN_Data16[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_PINTEN_Data17[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_PINTINV_Data18[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_PINCFG_Data19[1] =
{
	0x01u	
};

static unsigned char gaConfig_slave1_TESTMODE_Data20[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_CLK1CFG_Data21[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_CLK2CFG_Data22[1] =
{
	0x81u	
};

static unsigned char gaConfig_slave1_UPMASK0_Data23[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_UPMASK1_Data24[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_UPMASK2_Data25[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_UPMASK3_Data26[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_UPOFFSET_Data27[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_DNMASK0_Data28[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_DNMASK1_Data29[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_DNMASK2_Data30[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_DNMASK3_Data31[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_DNOFFSET_Data32[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_GPIOD0MSK_Data33[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_GPIOD1MSK_Data34[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_GPIOD2MSK_Data35[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_GPIOD3MSK_Data36[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_GPIOD4MSK_Data37[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_GPIOD5MSK_Data38[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_GPIOD6MSK_Data39[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_GPIOD7MSK_Data40[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_GPIODINV_Data41[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_GPIODEN_Data42[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_MBOX0CTL_Data43[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_MBOX1CTL_Data44[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_SUSCFG_Data45[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_I2SRRSOFFS_Data46[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_I2SRRCTL_Data47[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_TXACTL_Data48[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_TXBCTL_Data49[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_INTMSK0_Data50[1] =
{
	0x10u	
};

static unsigned char gaConfig_slave1_INTMSK1_Data51[1] =
{
	0x00u	
};

static unsigned char gaConfig_slave1_BECCTL_Data52[1] =
{
	0xEFu	
};

static unsigned char gaConfig_master_NODEADRSet_Data17[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_I2CCFG_Data18[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_I2SCFG_Data19[1] =
{
	0x7Fu	
};

static unsigned char gaConfig_master_I2STXOFFSET_Data20[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_I2SRXOFFSET_Data21[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_PDMCTL_Data22[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_PDMCTL2_Data23[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_ERRMGMT_Data24[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_GPIODAT_Data25[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_GPIOOEN_Data26[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_GPIOIEN_Data27[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_PINTEN_Data28[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_PINTINV_Data29[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_PINCFG_Data30[1] =
{
	0x01u	
};

static unsigned char gaConfig_master_TESTMODE_Data31[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_CLK1CFG_Data32[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_CLK2CFG_Data33[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_GPIOD0MSK_Data34[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_GPIOD1MSK_Data35[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_GPIOD2MSK_Data36[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_GPIOD3MSK_Data37[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_GPIOD4MSK_Data38[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_GPIOD5MSK_Data39[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_GPIOD6MSK_Data40[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_GPIOD7MSK_Data41[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_GPIODINV_Data42[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_GPIODEN_Data43[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_I2SRRCTL_Data44[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_TXACTL_Data45[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_TXBCTL_Data46[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_BECCTL_Data47[1] =
{
	0xEFu	
};

static unsigned char gaConfig_master_DNSLOTS_Data48[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_UPSLOTS_Data49[1] =
{
	0x04u	
};

static unsigned char gaConfig_master_SWCTL_Data50[1] =
{
	0x01u	
};

static unsigned char gaConfig_master_PLLCTL_Data51[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_NODEADR_Data52[1] =
{
	0x80u	
};

static unsigned char gaConfig_master_PLLCTL_Data53[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_NODEADR_Data54[1] =
{
	0x00u	
};

static unsigned char gaConfig_master_SLOTFMT_Data55[1] =
{
	0x44u	
};

static unsigned char gaConfig_master_DATCTL_Data56[1] =
{
	0x03u	
};

static unsigned char gaConfig_master_I2SRRATE_Data57[1] =
{
	0x01u	
};

static unsigned char gaConfig_master_CONTROL_Data58[1] =
{
	0x01u	
};

ADI_A2B_DISCOVERY_CONFIG gaA2BConfig[CONFIG_LEN] =
{

	/*-- COMMANDS FOR DEVICE - master --*/
	{0x68u,	WRITE,	0x01u,	0x00000012u,	0x01u,	0x0001u,	&gaConfig_master_CONTROL_Data0[0]},	/* CONTROL */
	{0x00u,	DELAY,	0x01u,	0x00000000u,	0x01u,	0x0001u,	&gaConfig_master_A2BDelay_Data1[0]},	/* A2B_Delay */
	{0x68u,	READ,	0x01u,	0x00000017u,	0x01u,	0x0001u,	&gaConfig_master_INTTYPE_Data2[0]},	/* INTTYPE */
	{0x68u,	WRITE,	0x01u,	0x0000001Bu,	0x01u,	0x0001u,	&gaConfig_master_INTMSK0_Data3[0]},	/* INTMSK0 */
	{0x68u,	WRITE,	0x01u,	0x0000001Cu,	0x01u,	0x0001u,	&gaConfig_master_INTMSK1_Data4[0]},	/* INTMSK1 */
	{0x68u,	WRITE,	0x01u,	0x0000001Du,	0x01u,	0x0001u,	&gaConfig_master_INTMSK2_Data5[0]},	/* INTMSK2 */
	{0x68u,	WRITE,	0x01u,	0x0000000Fu,	0x01u,	0x0001u,	&gaConfig_master_RESPCYCS_Data6[0]},	/* RESPCYCS */
	{0x68u,	WRITE,	0x01u,	0x00000012u,	0x01u,	0x0001u,	&gaConfig_master_CONTROL_Data7[0]},	/* CONTROL */
	{0x68u,	WRITE,	0x01u,	0x00000041u,	0x01u,	0x0001u,	&gaConfig_master_I2SGCFG_Data8[0]},	/* I2SGCFG */
	{0x68u,	WRITE,	0x01u,	0x00000009u,	0x01u,	0x0001u,	&gaConfig_master_SWCTL_Data9[0]},	/* SWCTL */
	{0x68u,	WRITE,	0x01u,	0x00000013u,	0x01u,	0x0001u,	&gaConfig_master_DISCVRY_Data10[0]},	/* DISCVRY */
	{0x00u,	DELAY,	0x01u,	0x00000000u,	0x01u,	0x0001u,	&gaConfig_master_A2BDelay_Data11[0]},	/* A2B_Delay */
	{0x68u,	READ,	0x01u,	0x0000001Au,	0x01u,	0x0001u,	&gaConfig_master_INTPND2_Data12[0]},	/* INTPND2 */
	{0x68u,	WRITE,	0x01u,	0x0000001Au,	0x01u,	0x0001u,	&gaConfig_master_INTPND2_Data13[0]},	/* INTPND2 */
	{0x68u,	WRITE,	0x01u,	0x00000001u,	0x01u,	0x0001u,	&gaConfig_master_NODEADR_Data14[0]},	/* NODEADR */

	/*-- COMMANDS FOR DEVICE - slave1 --*/
	{0x69u,	READ,	0x01u,	0x00000002u,	0x01u,	0x0001u,	&gaConfig_slave1_VENDOR_Data0[0]},	/* VENDOR */
	{0x69u,	READ,	0x01u,	0x00000003u,	0x01u,	0x0001u,	&gaConfig_slave1_PRODUCT_Data1[0]},	/* PRODUCT */
	{0x69u,	READ,	0x01u,	0x00000004u,	0x01u,	0x0001u,	&gaConfig_slave1_VERSION_Data2[0]},	/* VERSION */

	/*-- COMMANDS FOR DEVICE - master --*/
	{0x68u,	WRITE,	0x01u,	0x00000009u,	0x01u,	0x0001u,	&gaConfig_master_SWCTL_Data15[0]},	/* SWCTL */
	{0x68u,	WRITE,	0x01u,	0x00000001u,	0x01u,	0x0001u,	&gaConfig_master_NODEADR_Data16[0]},	/* NODEADR */

	/*-- COMMANDS FOR DEVICE - slave1 --*/
	{0x69u,	WRITE,	0x01u,	0x0000000Au,	0x01u,	0x0001u,	&gaConfig_slave1_BCDNSLOTS_Data3[0]},	/* BCDNSLOTS */
	{0x69u,	WRITE,	0x01u,	0x0000000Bu,	0x01u,	0x0001u,	&gaConfig_slave1_LDNSLOTS_Data4[0]},	/* LDNSLOTS */
	{0x69u,	WRITE,	0x01u,	0x0000000Cu,	0x01u,	0x0001u,	&gaConfig_slave1_LUPSLOTS_Data5[0]},	/* LUPSLOTS */
	{0x69u,	WRITE,	0x01u,	0x0000003Fu,	0x01u,	0x0001u,	&gaConfig_slave1_I2CCFG_Data6[0]},	/* I2CCFG */
	{0x69u,	WRITE,	0x01u,	0x00000046u,	0x01u,	0x0001u,	&gaConfig_slave1_SYNCOFFSET_Data7[0]},	/* SYNCOFFSET */
	{0x69u,	WRITE,	0x01u,	0x00000041u,	0x01u,	0x0001u,	&gaConfig_slave1_I2SGCFG_Data8[0]},	/* I2SGCFG */
	{0x69u,	WRITE,	0x01u,	0x00000042u,	0x01u,	0x0001u,	&gaConfig_slave1_I2SCFG_Data9[0]},	/* I2SCFG */
	{0x69u,	WRITE,	0x01u,	0x00000043u,	0x01u,	0x0001u,	&gaConfig_slave1_I2SRATE_Data10[0]},	/* I2SRATE */
	{0x69u,	WRITE,	0x01u,	0x00000047u,	0x01u,	0x0001u,	&gaConfig_slave1_PDMCTL_Data11[0]},	/* PDMCTL */
	{0x69u,	WRITE,	0x01u,	0x0000005Du,	0x01u,	0x0001u,	&gaConfig_slave1_PDMCTL2_Data12[0]},	/* PDMCTL2 */
	{0x69u,	WRITE,	0x01u,	0x00000048u,	0x01u,	0x0001u,	&gaConfig_slave1_ERRMGMT_Data13[0]},	/* ERRMGMT */
	{0x69u,	WRITE,	0x01u,	0x0000004Au,	0x01u,	0x0001u,	&gaConfig_slave1_GPIODAT_Data14[0]},	/* GPIODAT */
	{0x69u,	WRITE,	0x01u,	0x0000004Du,	0x01u,	0x0001u,	&gaConfig_slave1_GPIOOEN_Data15[0]},	/* GPIOOEN */
	{0x69u,	WRITE,	0x01u,	0x0000004Eu,	0x01u,	0x0001u,	&gaConfig_slave1_GPIOIEN_Data16[0]},	/* GPIOIEN */
	{0x69u,	WRITE,	0x01u,	0x00000050u,	0x01u,	0x0001u,	&gaConfig_slave1_PINTEN_Data17[0]},	/* PINTEN */
	{0x69u,	WRITE,	0x01u,	0x00000051u,	0x01u,	0x0001u,	&gaConfig_slave1_PINTINV_Data18[0]},	/* PINTINV */
	{0x69u,	WRITE,	0x01u,	0x00000052u,	0x01u,	0x0001u,	&gaConfig_slave1_PINCFG_Data19[0]},	/* PINCFG */
	{0x69u,	WRITE,	0x01u,	0x00000020u,	0x01u,	0x0001u,	&gaConfig_slave1_TESTMODE_Data20[0]},	/* TESTMODE */
	{0x69u,	WRITE,	0x01u,	0x00000059u,	0x01u,	0x0001u,	&gaConfig_slave1_CLK1CFG_Data21[0]},	/* CLK1CFG */
	{0x69u,	WRITE,	0x01u,	0x0000005Au,	0x01u,	0x0001u,	&gaConfig_slave1_CLK2CFG_Data22[0]},	/* CLK2CFG */
	{0x69u,	WRITE,	0x01u,	0x00000060u,	0x01u,	0x0001u,	&gaConfig_slave1_UPMASK0_Data23[0]},	/* UPMASK0 */
	{0x69u,	WRITE,	0x01u,	0x00000061u,	0x01u,	0x0001u,	&gaConfig_slave1_UPMASK1_Data24[0]},	/* UPMASK1 */
	{0x69u,	WRITE,	0x01u,	0x00000062u,	0x01u,	0x0001u,	&gaConfig_slave1_UPMASK2_Data25[0]},	/* UPMASK2 */
	{0x69u,	WRITE,	0x01u,	0x00000063u,	0x01u,	0x0001u,	&gaConfig_slave1_UPMASK3_Data26[0]},	/* UPMASK3 */
	{0x69u,	WRITE,	0x01u,	0x00000064u,	0x01u,	0x0001u,	&gaConfig_slave1_UPOFFSET_Data27[0]},	/* UPOFFSET */
	{0x69u,	WRITE,	0x01u,	0x00000065u,	0x01u,	0x0001u,	&gaConfig_slave1_DNMASK0_Data28[0]},	/* DNMASK0 */
	{0x69u,	WRITE,	0x01u,	0x00000066u,	0x01u,	0x0001u,	&gaConfig_slave1_DNMASK1_Data29[0]},	/* DNMASK1 */
	{0x69u,	WRITE,	0x01u,	0x00000067u,	0x01u,	0x0001u,	&gaConfig_slave1_DNMASK2_Data30[0]},	/* DNMASK2 */
	{0x69u,	WRITE,	0x01u,	0x00000068u,	0x01u,	0x0001u,	&gaConfig_slave1_DNMASK3_Data31[0]},	/* DNMASK3 */
	{0x69u,	WRITE,	0x01u,	0x00000069u,	0x01u,	0x0001u,	&gaConfig_slave1_DNOFFSET_Data32[0]},	/* DNOFFSET */
	{0x69u,	WRITE,	0x01u,	0x00000081u,	0x01u,	0x0001u,	&gaConfig_slave1_GPIOD0MSK_Data33[0]},	/* GPIOD0MSK */
	{0x69u,	WRITE,	0x01u,	0x00000082u,	0x01u,	0x0001u,	&gaConfig_slave1_GPIOD1MSK_Data34[0]},	/* GPIOD1MSK */
	{0x69u,	WRITE,	0x01u,	0x00000083u,	0x01u,	0x0001u,	&gaConfig_slave1_GPIOD2MSK_Data35[0]},	/* GPIOD2MSK */
	{0x69u,	WRITE,	0x01u,	0x00000084u,	0x01u,	0x0001u,	&gaConfig_slave1_GPIOD3MSK_Data36[0]},	/* GPIOD3MSK */
	{0x69u,	WRITE,	0x01u,	0x00000085u,	0x01u,	0x0001u,	&gaConfig_slave1_GPIOD4MSK_Data37[0]},	/* GPIOD4MSK */
	{0x69u,	WRITE,	0x01u,	0x00000086u,	0x01u,	0x0001u,	&gaConfig_slave1_GPIOD5MSK_Data38[0]},	/* GPIOD5MSK */
	{0x69u,	WRITE,	0x01u,	0x00000087u,	0x01u,	0x0001u,	&gaConfig_slave1_GPIOD6MSK_Data39[0]},	/* GPIOD6MSK */
	{0x69u,	WRITE,	0x01u,	0x00000088u,	0x01u,	0x0001u,	&gaConfig_slave1_GPIOD7MSK_Data40[0]},	/* GPIOD7MSK */
	{0x69u,	WRITE,	0x01u,	0x0000008Au,	0x01u,	0x0001u,	&gaConfig_slave1_GPIODINV_Data41[0]},	/* GPIODINV */
	{0x69u,	WRITE,	0x01u,	0x00000080u,	0x01u,	0x0001u,	&gaConfig_slave1_GPIODEN_Data42[0]},	/* GPIODEN */
	{0x69u,	WRITE,	0x01u,	0x00000090u,	0x01u,	0x0001u,	&gaConfig_slave1_MBOX0CTL_Data43[0]},	/* MBOX0CTL */
	{0x69u,	WRITE,	0x01u,	0x00000096u,	0x01u,	0x0001u,	&gaConfig_slave1_MBOX1CTL_Data44[0]},	/* MBOX1CTL */
	{0x69u,	WRITE,	0x01u,	0x0000005Cu,	0x01u,	0x0001u,	&gaConfig_slave1_SUSCFG_Data45[0]},	/* SUSCFG */
	{0x69u,	WRITE,	0x01u,	0x00000058u,	0x01u,	0x0001u,	&gaConfig_slave1_I2SRRSOFFS_Data46[0]},	/* I2SRRSOFFS */
	{0x69u,	WRITE,	0x01u,	0x00000057u,	0x01u,	0x0001u,	&gaConfig_slave1_I2SRRCTL_Data47[0]},	/* I2SRRCTL */
	{0x69u,	WRITE,	0x01u,	0x0000002Eu,	0x01u,	0x0001u,	&gaConfig_slave1_TXACTL_Data48[0]},	/* TXACTL */
	{0x69u,	WRITE,	0x01u,	0x00000030u,	0x01u,	0x0001u,	&gaConfig_slave1_TXBCTL_Data49[0]},	/* TXBCTL */
	{0x69u,	WRITE,	0x01u,	0x0000001Bu,	0x01u,	0x0001u,	&gaConfig_slave1_INTMSK0_Data50[0]},	/* INTMSK0 */
	{0x69u,	WRITE,	0x01u,	0x0000001Cu,	0x01u,	0x0001u,	&gaConfig_slave1_INTMSK1_Data51[0]},	/* INTMSK1 */
	{0x69u,	WRITE,	0x01u,	0x0000001Eu,	0x01u,	0x0001u,	&gaConfig_slave1_BECCTL_Data52[0]},	/* BECCTL */

	/*-- COMMANDS FOR DEVICE - master --*/
	{0x68u,	WRITE,	0x01u,	0x00000001u,	0x01u,	0x0001u,	&gaConfig_master_NODEADRSet_Data17[0]},	/* NODEADR - Set the node address */
	{0x68u,	WRITE,	0x01u,	0x0000003Fu,	0x01u,	0x0001u,	&gaConfig_master_I2CCFG_Data18[0]},	/* I2CCFG */
	{0x68u,	WRITE,	0x01u,	0x00000042u,	0x01u,	0x0001u,	&gaConfig_master_I2SCFG_Data19[0]},	/* I2SCFG */
	{0x68u,	WRITE,	0x01u,	0x00000044u,	0x01u,	0x0001u,	&gaConfig_master_I2STXOFFSET_Data20[0]},	/* I2STXOFFSET */
	{0x68u,	WRITE,	0x01u,	0x00000045u,	0x01u,	0x0001u,	&gaConfig_master_I2SRXOFFSET_Data21[0]},	/* I2SRXOFFSET */
	{0x68u,	WRITE,	0x01u,	0x00000047u,	0x01u,	0x0001u,	&gaConfig_master_PDMCTL_Data22[0]},	/* PDMCTL */
	{0x68u,	WRITE,	0x01u,	0x0000005Du,	0x01u,	0x0001u,	&gaConfig_master_PDMCTL2_Data23[0]},	/* PDMCTL2 */
	{0x68u,	WRITE,	0x01u,	0x00000048u,	0x01u,	0x0001u,	&gaConfig_master_ERRMGMT_Data24[0]},	/* ERRMGMT */
	{0x68u,	WRITE,	0x01u,	0x0000004Au,	0x01u,	0x0001u,	&gaConfig_master_GPIODAT_Data25[0]},	/* GPIODAT */
	{0x68u,	WRITE,	0x01u,	0x0000004Du,	0x01u,	0x0001u,	&gaConfig_master_GPIOOEN_Data26[0]},	/* GPIOOEN */
	{0x68u,	WRITE,	0x01u,	0x0000004Eu,	0x01u,	0x0001u,	&gaConfig_master_GPIOIEN_Data27[0]},	/* GPIOIEN */
	{0x68u,	WRITE,	0x01u,	0x00000050u,	0x01u,	0x0001u,	&gaConfig_master_PINTEN_Data28[0]},	/* PINTEN */
	{0x68u,	WRITE,	0x01u,	0x00000051u,	0x01u,	0x0001u,	&gaConfig_master_PINTINV_Data29[0]},	/* PINTINV */
	{0x68u,	WRITE,	0x01u,	0x00000052u,	0x01u,	0x0001u,	&gaConfig_master_PINCFG_Data30[0]},	/* PINCFG */
	{0x68u,	WRITE,	0x01u,	0x00000020u,	0x01u,	0x0001u,	&gaConfig_master_TESTMODE_Data31[0]},	/* TESTMODE */
	{0x68u,	WRITE,	0x01u,	0x00000059u,	0x01u,	0x0001u,	&gaConfig_master_CLK1CFG_Data32[0]},	/* CLK1CFG */
	{0x68u,	WRITE,	0x01u,	0x0000005Au,	0x01u,	0x0001u,	&gaConfig_master_CLK2CFG_Data33[0]},	/* CLK2CFG */
	{0x68u,	WRITE,	0x01u,	0x00000081u,	0x01u,	0x0001u,	&gaConfig_master_GPIOD0MSK_Data34[0]},	/* GPIOD0MSK */
	{0x68u,	WRITE,	0x01u,	0x00000082u,	0x01u,	0x0001u,	&gaConfig_master_GPIOD1MSK_Data35[0]},	/* GPIOD1MSK */
	{0x68u,	WRITE,	0x01u,	0x00000083u,	0x01u,	0x0001u,	&gaConfig_master_GPIOD2MSK_Data36[0]},	/* GPIOD2MSK */
	{0x68u,	WRITE,	0x01u,	0x00000084u,	0x01u,	0x0001u,	&gaConfig_master_GPIOD3MSK_Data37[0]},	/* GPIOD3MSK */
	{0x68u,	WRITE,	0x01u,	0x00000085u,	0x01u,	0x0001u,	&gaConfig_master_GPIOD4MSK_Data38[0]},	/* GPIOD4MSK */
	{0x68u,	WRITE,	0x01u,	0x00000086u,	0x01u,	0x0001u,	&gaConfig_master_GPIOD5MSK_Data39[0]},	/* GPIOD5MSK */
	{0x68u,	WRITE,	0x01u,	0x00000087u,	0x01u,	0x0001u,	&gaConfig_master_GPIOD6MSK_Data40[0]},	/* GPIOD6MSK */
	{0x68u,	WRITE,	0x01u,	0x00000088u,	0x01u,	0x0001u,	&gaConfig_master_GPIOD7MSK_Data41[0]},	/* GPIOD7MSK */
	{0x68u,	WRITE,	0x01u,	0x0000008Au,	0x01u,	0x0001u,	&gaConfig_master_GPIODINV_Data42[0]},	/* GPIODINV */
	{0x68u,	WRITE,	0x01u,	0x00000080u,	0x01u,	0x0001u,	&gaConfig_master_GPIODEN_Data43[0]},	/* GPIODEN */
	{0x68u,	WRITE,	0x01u,	0x00000057u,	0x01u,	0x0001u,	&gaConfig_master_I2SRRCTL_Data44[0]},	/* I2SRRCTL */
	{0x68u,	WRITE,	0x01u,	0x0000002Eu,	0x01u,	0x0001u,	&gaConfig_master_TXACTL_Data45[0]},	/* TXACTL */
	{0x68u,	WRITE,	0x01u,	0x00000030u,	0x01u,	0x0001u,	&gaConfig_master_TXBCTL_Data46[0]},	/* TXBCTL */
	{0x68u,	WRITE,	0x01u,	0x0000001Eu,	0x01u,	0x0001u,	&gaConfig_master_BECCTL_Data47[0]},	/* BECCTL */
	{0x68u,	WRITE,	0x01u,	0x0000000Du,	0x01u,	0x0001u,	&gaConfig_master_DNSLOTS_Data48[0]},	/* DNSLOTS */
	{0x68u,	WRITE,	0x01u,	0x0000000Eu,	0x01u,	0x0001u,	&gaConfig_master_UPSLOTS_Data49[0]},	/* UPSLOTS */
	{0x68u,	WRITE,	0x01u,	0x00000009u,	0x01u,	0x0001u,	&gaConfig_master_SWCTL_Data50[0]},	/* SWCTL */
	{0x68u,	WRITE,	0x01u,	0x00000040u,	0x01u,	0x0001u,	&gaConfig_master_PLLCTL_Data51[0]},	/* PLLCTL */
	{0x68u,	WRITE,	0x01u,	0x00000001u,	0x01u,	0x0001u,	&gaConfig_master_NODEADR_Data52[0]},	/* NODEADR */

	/*-- COMMANDS FOR DEVICE - master --*/
	{0x69u,	WRITE,	0x01u,	0x00000040u,	0x01u,	0x0001u,	&gaConfig_master_PLLCTL_Data53[0]},	/* PLLCTL */

	/*-- COMMANDS FOR DEVICE - master --*/
	{0x68u,	WRITE,	0x01u,	0x00000001u,	0x01u,	0x0001u,	&gaConfig_master_NODEADR_Data54[0]},	/* NODEADR */
	{0x68u,	WRITE,	0x01u,	0x00000010u,	0x01u,	0x0001u,	&gaConfig_master_SLOTFMT_Data55[0]},	/* SLOTFMT */
	{0x68u,	WRITE,	0x01u,	0x00000011u,	0x01u,	0x0001u,	&gaConfig_master_DATCTL_Data56[0]},	/* DATCTL */
	{0x68u,	WRITE,	0x01u,	0x00000056u,	0x01u,	0x0001u,	&gaConfig_master_I2SRRATE_Data57[0]},	/* I2SRRATE */
	{0x68u,	WRITE,	0x01u,	0x00000012u,	0x01u,	0x0001u,	&gaConfig_master_CONTROL_Data58[0]},	/* CONTROL */
};

#endif /* _ADI_A2B_I2C_LIST_H_ */

In order to include this personalized A2B configuration in the CCES project, I managed to add the file inside the file audio_framework_8ch_sam_and_audioproj_fin_arm.c .

Also I decided to use processing only on Core 1 (putting the macro USE_BOTH_CORES_TO_PROCESS_AUDIO to false). 

In the following I attach the callback_audio_processing.cpp of Core 1.

/*
 * Copyright (c) 2018-2019 Analog Devices, Inc.  All rights reserved.
 *
 * These are the hooks for the audio processing functions.
 *
 */

#include <audio_processing/audio_effects_selector.h>
#include <math.h>

// Define your audio system parameters in this file
#include "common/audio_system_config.h"

// Support for simple multi-core data sharing
#include "common/multicore_shared_memory.h"

// Variables related to the audio framework that is currently selected (e.g. input and output buffers)
#include "audio_framework_selector.h"

// Includes all header files for effects and calls for effect selector
#include "audio_processing/audio_effects_selector.h"

// Prototypes for this file
#include "callback_audio_processing.h"

/*
 *
 * Available Processing Power
 * --------------------------
 *
 * The two SHARC cores provide a hefty amount of audio processing power.  However, it is
 * important to ensure that any audio processing code can run and complete within one frame of audio.
 *
 * The total number of cycles available in the audio callback can be calculated as follows:
 *
 * total cycles = ( processor-clock-speed * audio-block-size ) / audio-sample-rate//
 *
 * For example, if the processor is running at 450MHz, the audio sampling rate is 48KHz and the
 * audio block size is set to 32 words, the total number of processor cycles available in each
 * callback is 300,000 cycles or 300,000/32 or 9,375 per sample of audio.
 *
 * Available Audio Buffers
 * -----------------------
 *
 * There are several sets of audio input and output buffers that correspond to the
 * various peripherals (e.g. audio codec, USB, S/PDIF, A2B).
 *
 * To send audio from USB out the DAC on the ADAU1761 one simply needs to copy data
 * from the USB buffers and copy them to the ADAU1761 buffer.
 *
 * for (i=0;i<AUDIO_BLOCK_SIZE;i++) {
 *   audiochannel_adau1761_0_left_out[i] = audiochannel_USB_0_left_in[i];
 *   audiochannel_adau1761_0_right_out[i] = audiochannel_USB_0_right_in[i];
 * }
 *
 * The framework ensures that audio is sample rate converted as needed (e.g S/PDIF)
 * and arrives where it needs to be on time using DMA.  It also manages the conversion
 * between fixed and floating point.
 *
 * Below is a list of the various input buffers and output buffers that are available.
 * Be sure that the corresponding peripheral has been enabled in audio_system_config.h
 *
 * Input Buffers
 * *************
 *
 *  Audio from the ADAU1761 ADCs
 *     audiochannel_adau1761_0_left_in[]
 *     audiochannel_adau1761_0_left_in[]
 *
 *  Audio from the S/PDIF receiver
 *     audiochannel_spdif_0_left_in[]
 *     audiochannel_spdif_0_right_in[]
 *
 *  Audio from USB (be sure to enable USB in audio_system_config.h)
 *     audiochannel_USB_0_left_in[]
 *     audiochannel_USB_0_right_in[]
 *
 *  Audio from A2B Bus
 *     audiochannel_a2b_0_left_in[]
 *     audiochannel_a2b_0_right_in[]
 *     audiochannel_a2b_1_left_in[]
 *     audiochannel_a2b_1_right_in[]
 *     audiochannel_a2b_2_left_in[]
 *     audiochannel_a2b_2_right_in[]
 *     audiochannel_a2b_3_left_in[]
 *     audiochannel_a2b_3_right_in[]
 *
 *
 *  Audio from Faust (be sure to enable Faust in audio_system_config.h and include the libraries)
 *
 *     audioChannel_faust_0_left_in[]
 *     audioChannel_faust_0_right_in[]
 *     audioChannel_faust_1_left_in[]
 *     audioChannel_faust_1_right_in[]
 *     audioChannel_faust_2_left_in[]
 *     audioChannel_faust_2_right_in[]
 *     audioChannel_faust_3_left_in[]
 *     audioChannel_faust_3_right_in[]
 *
 * Output Buffers
 * **************
 *  Audio to the ADAU1761 DACs
 *     audiochannel_adau1761_0_left_out[]
 *     audiochannel_adau1761_0_left_out[]
 *
 *  Audio to the S/PDIF transmitter
 *     audiochannel_spdif_0_left_out[]
 *     audiochannel_spdif_0_right_out[]
 *
 *  Audio to USB (be sure to enable USB in audio_system_config.h)
 *     audiochannel_USB_0_left_out[]
 *     audiochannel_USB_0_right_out[]
 *
 *  Audio to A2B Bus (be sure to enable A2B in audio_system_config.h)
 *     audiochannel_a2b_0_left_out[]
 *     audiochannel_a2b_0_right_out[]
 *     audiochannel_a2b_1_left_out[]
 *     audiochannel_a2b_1_right_out[]
 *     audiochannel_a2b_2_left_out[]
 *     audiochannel_a2b_2_right_out[]
 *     audiochannel_a2b_3_left_out[]
 *     audiochannel_a2b_3_right_out[]
 *
 *  Audio from Faust (be sure to enable Faust in audio_system_config.h)
 *
 *     audioChannel_faust_0_left_out[]
 *     audioChannel_faust_0_right_out[]
 *     audioChannel_faust_1_left_out[]
 *     audioChannel_faust_1_right_out[]
 *     audioChannel_faust_2_left_out[]
 *     audioChannel_faust_2_right_out[]
 *     audioChannel_faust_3_left_out[]
 *     audioChannel_faust_3_right_out[]
 *
 *  Note: Faust processing occurs before the audio callback so any data
 *  copied into Faust's input buffers will be available the next time
 *  the callback is called.  Similarly, Faust's output buffers contain
 *  audio that was processed before the callback.
 *
 *
 * There is also a set of buffers for sending audio to / from SHARC Core 2
 *
 *  Output to SHARC Core 2
 *     audiochannel_to_sharc_core2_0_left[]
 *     audiochannel_to_sharc_core2_0_right[]
 *     audiochannel_to_sharc_core2_1_left[]
 *     audiochannel_to_sharc_core2_1_right[]
 *     audiochannel_to_sharc_core2_2_left[]
 *     audiochannel_to_sharc_core2_2_right[]
 *     audiochannel_to_sharc_core2_3_left[]
 *     audiochannel_to_sharc_core2_3_right[]
 *
 *  Input from SHARC Core 2 (processed audio from SHARC Core 2)
 *     audiochannel_from_sharc_core2_0_left[]
 *     audiochannel_from_sharc_core2_0_right[]
 *     audiochannel_from_sharc_core2_1_left[]
 *     audiochannel_from_sharc_core2_1_right[]
 *     audiochannel_from_sharc_core2_2_left[]
 *     audiochannel_from_sharc_core2_2_right[]
 *     audiochannel_from_sharc_core2_3_left[]
 *     audiochannel_from_sharc_core2_3_right[]
 *
 * Finally, there is a set of aliased buffers that sends audio to the
 * right place.  On SHARC 1, the In[] buffers are received from the ADC
 * and the Out[] buffers are sent to either SHARC 2 (when in dual core more)
 * or to the DACs (when in single core mode).  The In[] buffers on SHARC core
 * 2 are received from SHARC core 1 and the Out[] buffers are sent to the DACs
 * (via SHARC core 1).
 *
 *     audiochannel_0_left_in[]
 *     audiochannel_0_right_in[]
 *
 *     audiochannel_1_left_out[]
 *     audiochannel_1_right_out[]
 *     audiochannel_2_left_out[]
 *     audiochannel_2_right_out[]
 *     audiochannel_3_left_out[]
 *     audiochannel_3_right_out[]
 *
 *     When the automotive board is being used, there are 16 channels of aliased
 *     buffers, not 8.  So they go up to audiochannel_7_left_in / audiochannel_7_right_in
 *     and audiochannel_7_left_out / audiochannel_7_right_out
 *
 * See the .c/.h file for the corresponding audio framework in the Audio_Frameworks
 * directory to see the buffers that are available for other frameworks (like the
 * 16 channel automotive framework).
 *
 */

/*
 * Place any initialization code here for the audio processing
 */
void processaudio_setup(void) {

	// Initialize the audio effects in the audio_processing/ folder
	audio_effects_setup_core1();

	// *******************************************************************************
	// Add any custom setup code here
	// *******************************************************************************

}

/*
 * This callback is called every time we have a new audio buffer that is ready
 * for processing.  It's currently configured for in-place processing so if no
 * processing is done to the audio, it is passed through unaffected.
 *
 * See the header file for the framework you have selected in the Audio_Frameworks
 * directory for a list of the input and output buffers that are available based on
 * the framework and hardware.
 *
 * The two SHARC cores provide a hefty amount of audio processing power. However, it is important
 * to ensure that any audio processing code can run and complete within one frame of audio.
 *
 * The total number of cycles available in the audio callback can be calculated as follows:
 * total cycles = ( processor-clock-speed * audio-block-size ) / audio-sample-rate
 *
 * For example, if the processor is running at 450MHz, the audio sampling rate is 48KHz and the audio
 * block size is set to 32 words, the total number of processor cycles available in each callback
 * is 300,000 cycles or 300,000/32 or 9,375 per sample of audio
 */

// When debugging audio algorithms, helpful to comment out this pragma for more linear single stepping.
#pragma optimize_for_speed
void processaudio_callback(void) {

	if (false) {

		// Copy incoming audio buffers to the effects input buffers
		copy_buffer(audiochannel_0_left_in, audio_effects_left_in,
				AUDIO_BLOCK_SIZE);
		copy_buffer(audiochannel_0_right_in, audio_effects_right_in,
				AUDIO_BLOCK_SIZE);

		// Process audio effects
		audio_effects_process_audio_core1();

		// Copy processed audio back to input buffers
		copy_buffer(audio_effects_left_out, audiochannel_0_left_in,
				AUDIO_BLOCK_SIZE);
		copy_buffer(audio_effects_right_out, audiochannel_0_right_in,
				AUDIO_BLOCK_SIZE);

	}

	// Otherwise, perform our C-based block processing here!
	for (int i = 0; i < AUDIO_BLOCK_SIZE; i++) {

		// *******************************************************************************
		// Replace the pass-through code below with your custom audio processing code here
		// *******************************************************************************

		// Default: Pass audio just from 1/8" (or 1/4" on Audio Project Fin) inputs to outputs (jack)

		//audiochannel_0_left_out[i] = audiochannel_0_left_in[i];
		//audiochannel_0_right_out[i] = audiochannel_0_right_in[i];

		/* Below are some additional examples of how to receive audio from the various input buffers

		 // Example: Pass audio just from 1/8" (or 1/4" on Audio Project Fin) inputs to outputs
		 audioChannel_0_left_out[i] = audioChannel_0_left_in[i];
		 audioChannel_0_right_out[i] = AudioChannel_0_right_in[i];

		 // Example: mix audio in from 1/8" jacks and A2B input
		 audiochannel_0_left_out[i] = audiochannel_0_left_in[i] + audiochannel_a2b_0_left_in[i];
		 audiochannel_0_right_out[i] = audiochannel_0_right_in[i] + audiochannel_a2b_0_right_in[i];

		 // Example: receive audio from S/PDIF inputs and analog inputs
		 audiochannel_0_left_out[i] = audiochannel_0_left_in[i] + audiochannel_spdif_0_left_in[i];
		 audiochannel_0_right_out[i] = audiochannel_0_right_in[i] + audiochannel_spdif_0_right_in[i];

		 */

		/* You can also write directly to the various output buffers to explicitly route
		 * audio to different peripherals (ADAU1761, S/PDIF, A2B, etc.).  If you're using both
		 * cores to process audio (configured in common/audio_system_config.h), write your
		 * processed audio data to the audiochannel_N_left_out/audiochannel_N_right_out buffers
		 * and direct the output to the second core.  The function below, processAudio_OutputRouting(),
		 * is then used to route audio returning from the second core to various peripherals.
		 *
		 * However, if you're only using a single core in the audio processing path, you can redirect audio to
		 * specific peripherals by writing to the corresponding output buffers as shown in the
		 * examples below.  When using just one core for processing, audio written to the
		 * audiochannel_0_left_out/audiochannel_0_right_out buffers will get sent to the ADAU1761.

		 // Example: Send audio in from ADAU1761 to the A2B bus (be sure to enable A2B in audio_system_config.h)
		 audiochannel_a2b_0_left_out[i] = audiochannel_0_left_in[i];
		 audiochannel_a2b_0_right_out[i] = audiochannel_0_right_in[i];

		 // Example: Send audio from ADAU1761 to the SPDIF transmitter
		 audiochannel_spdif_0_left_out[i]  = audiochannel_adau1761_0_left_in[i];
		 audiochannel_spdif_0_right_out[i] = audiochannel_adau1761_0_right_in[i];
		*/
		 // Example: Send first stereo pair from A2B bus to ADAU1761 audio out
		 audiochannel_adau1761_0_left_out[i] = audiochannel_a2b_0_left_in[i];
		 audiochannel_adau1761_0_right_out[i] = audiochannel_a2b_0_right_in[i];


   		// If we're using just one core and A2B is enabled, copy the output buffer to A2B bus as well
#if (!USE_BOTH_CORES_TO_PROCESS_AUDIO) && (ENABLE_A2B)
			audiochannel_a2b_0_left_out[i] = audiochannel_0_left_out[i];
			audiochannel_a2b_0_right_out[i] = audiochannel_0_right_out[i];
			audiochannel_a2b_1_left_out[i] = audiochannel_1_left_out[i];
			audiochannel_a2b_1_right_out[i] = audiochannel_1_right_out[i];
#endif

		// If we're using Faust, copy audio into the flow
#if (USE_FAUST_ALGORITHM_CORE1)

		// Copy 8 channel audio from Faust to output buffers
		audiochannel_0_left_out[i] = audioChannel_faust_0_left_out[i];
		audiochannel_0_right_out[i] = audioChannel_faust_0_right_out[i];
		audiochannel_1_left_out[i] = audioChannel_faust_1_left_out[i];
		audiochannel_1_right_out[i] = audioChannel_faust_1_right_out[i];
		audiochannel_2_left_out[i] = audioChannel_faust_2_left_out[i];
		audiochannel_2_right_out[i] = audioChannel_faust_2_right_out[i];
		audiochannel_3_left_out[i] = audioChannel_faust_3_left_out[i];
		audiochannel_3_right_out[i] = audioChannel_faust_3_right_out[i];

		// Route audio to Faust for next block
		audioChannel_faust_0_left_in[i] = audiochannel_0_left_in[i] + audiochannel_spdif_0_left_in[i];
		audioChannel_faust_0_right_in[i] = audiochannel_0_right_in[i] + audiochannel_spdif_0_right_in[i];

#endif
	}

}

#if (USE_BOTH_CORES_TO_PROCESS_AUDIO)

/*
 * When using a dual core configuration, SHARC Core 1 is responsible for routing the
 * processed audio from SHARC Core 2 to the various output buffers for the
 * devices connected to the SC589.  For example, in a dual core framework, SHARC Core 1
 * may pass 8 channels of audio to Core 2, and then receive 8 channels of processed audio
 * back from Core 2.  It is this routine where we route these channels to the ADAU1761,
 * the A2B bus, SPDIF, etc.
 */
#pragma optimize_for_speed
void processaudio_output_routing(void) {

	static float t = 0;

	for (int i = 0; i < AUDIO_BLOCK_SIZE; i++) {

		// If automotive board is attached, send all 16 channels from core 2 to the DACs
#if defined(AUDIO_FRAMEWORK_16CH_SAM_AND_AUTOMOTIVE_FIN) && AUDIO_FRAMEWORK_16CH_SAM_AND_AUTOMOTIVE_FIN

		// Copy 16 channels from Core 2 to the DACs on the automotive board
		audiochannel_automotive_0_left_out[i] = audiochannel_from_sharc_core2_0_left[i];
		audiochannel_automotive_0_right_out[i] = audiochannel_from_sharc_core2_0_right[i];
		audiochannel_automotive_1_left_out[i] = audiochannel_from_sharc_core2_1_left[i];
		audiochannel_automotive_1_right_out[i] = audiochannel_from_sharc_core2_1_right[i];
		audiochannel_automotive_2_left_out[i] = audiochannel_from_sharc_core2_2_left[i];
		audiochannel_automotive_2_right_out[i] = audiochannel_from_sharc_core2_2_right[i];
		audiochannel_automotive_3_left_out[i] = audiochannel_from_sharc_core2_3_left[i];
		audiochannel_automotive_3_right_out[i] = audiochannel_from_sharc_core2_3_right[i];
		audiochannel_automotive_4_left_out[i] = audiochannel_from_sharc_core2_4_left[i];
		audiochannel_automotive_4_right_out[i] = audiochannel_from_sharc_core2_4_right[i];
		audiochannel_automotive_5_left_out[i] = audiochannel_from_sharc_core2_5_left[i];
		audiochannel_automotive_5_right_out[i] = audiochannel_from_sharc_core2_5_right[i];
		audiochannel_automotive_6_left_out[i] = audiochannel_from_sharc_core2_6_left[i];
		audiochannel_automotive_6_right_out[i] = audiochannel_from_sharc_core2_6_right[i];
		audiochannel_automotive_7_left_out[i] = audiochannel_from_sharc_core2_7_left[i];
		audiochannel_automotive_7_right_out[i] = audiochannel_from_sharc_core2_7_right[i];

#else

		// If A2B enabled, route audio down the A2B bus
#if (ENABLE_A2B)

		// Send all 8 channels from core 2 down the A2B bus
//		audiochannel_a2b_0_left_out[i] = audiochannel_from_sharc_core2_0_left[i];
//		audiochannel_a2b_0_right_out[i] = audiochannel_from_sharc_core2_0_right[i];
//		audiochannel_a2b_1_left_out[i] = audiochannel_from_sharc_core2_1_left[i];
//		audiochannel_a2b_1_right_out[i] = audiochannel_from_sharc_core2_1_right[i];
//		audiochannel_a2b_2_left_out[i] = audiochannel_from_sharc_core2_2_left[i];
//		audiochannel_a2b_2_right_out[i] = audiochannel_from_sharc_core2_2_right[i];
//		audiochannel_a2b_3_left_out[i] = audiochannel_from_sharc_core2_3_left[i];
//		audiochannel_a2b_3_right_out[i] = audiochannel_from_sharc_core2_3_right[i];

#endif

		// Send Audio from SHARC Core 2 out to the DACs (1/8" audio out connector)
		audiochannel_adau1761_0_left_out[i] = audiochannel_from_sharc_core2_0_left[i];
		audiochannel_adau1761_0_right_out[i] = audiochannel_from_sharc_core2_0_right[i];

		// Send audio from SHARC Core 2 to the SPDIF transmitter as well
		audiochannel_spdif_0_left_out[i] =
				audiochannel_from_sharc_core2_0_left[i];
		audiochannel_spdif_0_right_out[i] =
				audiochannel_from_sharc_core2_0_right[i];
#endif
	}
}
#endif

/*
 * This loop function is like a thread with a low priority.  This is good place to process
 * large FFTs in the background without interrupting the audio processing callback.
 */
void processaudio_background_loop(void) {

	// *******************************************************************************
	// Add any custom background processing here
	// *******************************************************************************

}

/*
 * This function is called if the code in the audio processing callback takes too long
 * to complete (essentially exceeding the available computational resources of this core).
 */
void processaudio_mips_overflow(void) {
}

In order to listen the first two channels in the headphones I decommented the lines 296-297 and commented the lines 256-257. I also eliminated the audio processing.

The code compiles properly without any warning or error. The audio from the first two channels is cleary heard in the headphones. However, when I try to listen the other two channels I get no sound. In order to do so I changed the lines 296-297 like:

audiochannel_adau1761_0_left_out[i] = audiochannel_a2b_1_left_in[i];
audiochannel_adau1761_0_right_out[i] = audiochannel_a2b_1_right_in[i];

If anyone helps me it would be great. If needed I can provide the full CCES project of SigmaStudio file.

Thank You