Hi,
I use 2 AD2428s, one is _master and another is _slave. My MCU config the A2B using I2C interface to the _master chip.
The datas send to the _master chip is export from sigmastudio, and after MCU send config datas, the A2B system works well.
My question is in the config datas export from sigmastudio, you can see in the line 5,15,18,19,20, there are some read instructions, so I read datas from _master chip and then compare the datas read out to make sure if the A2B system works well. When I read the INTTYPE(0x17) and INTPND2(0x1A) registers, I can get the correct datas every time I read. However when I read VENDOR(0x02), PRODUCT(0x03) and VERSION(0x04) registers, I get error datas sometimes. The three datas will be error ramdomly, sometimes is from VENDOR(0x02), sometimes is from PRODUCT(0x03), sometimes is from VERSION(0x04), or sometimes is the mix of the three.
Although the datas read out may be error, the TDM tx and rx is already works, so i2c read maybe error but i2c write is normal. But why the error is always from the three registers not the other 2 registers?
I'm also interested in if there are some other methods to make sure the A2B system works well rather than read from the registers.
Another question is in line 4, there is a delay instruction, the value is 0x19, how much time should I delay, 0x19us or 0x19ms or other time?
ADI_A2B_DISCOVERY_CONFIG code gaA2BConfig[CONFIG_LEN] =
{
{0x68u, WRITE, 0x12u, 0x84u}, /* CONTROL */
{0x00u, DELAY, 0x00u, 0x19u}, /* A2B_Delay */
{0x68u, READ, 0x17u, 0xFFu}, /* INTTYPE */
{0x68u, WRITE, 0x1Bu, 0x10u}, /* INTMSK0 */
{0x68u, WRITE, 0x1Cu, 0x00u}, /* INTMSK1 */
{0x68u, WRITE, 0x1Du, 0x09u}, /* INTMSK2 */
{0x68u, WRITE, 0x0Fu, 0x7Du}, /* RESPCYCS */
{0x68u, WRITE, 0x12u, 0x01u}, /* CONTROL */
{0x68u, WRITE, 0x41u, 0x44u}, /* I2SGCFG */
{0x68u, WRITE, 0x09u, 0x01u}, /* SWCTL */
{0x68u, WRITE, 0x13u, 0x7Du}, /* DISCVRY */
{0x00u, DELAY, 0x00u, 0x32u}, /* A2B_Delay */
{0x68u, READ, 0x1Au, 0x01u}, /* INTPND2 */
{0x68u, WRITE, 0x1Au, 0x01u}, /* INTPND2 */
{0x68u, WRITE, 0x01u, 0x00u}, /* NODEADR */
{0x69u, READ, 0x02u, 0x00u}, /* VENDOR */
{0x69u, READ, 0x03u, 0x00u}, /* PRODUCT */
{0x69u, READ, 0x04u, 0x00u}, /* VERSION */
{0x68u, WRITE, 0x09u, 0x21u}, /* SWCTL */
{0x68u, WRITE, 0x01u, 0x00u}, /* NODEADR */
{0x69u, WRITE, 0x0Au, 0x00u}, /* BCDNSLOTS */
{0x69u, WRITE, 0x0Bu, 0x10u}, /* LDNSLOTS */
{0x69u, WRITE, 0x0Cu, 0x10u}, /* LUPSLOTS */
{0x69u, WRITE, 0x3Fu, 0x01u}, /* I2CCFG */
{0x69u, WRITE, 0x46u, 0x00u}, /* SYNCOFFSET */
{0x69u, WRITE, 0x41u, 0xE4u}, /* I2SGCFG */
{0x69u, WRITE, 0x42u, 0x19u}, /* I2SCFG */
{0x69u, WRITE, 0x43u, 0x00u}, /* I2SRATE */
{0x69u, WRITE, 0x47u, 0x18u}, /* PDMCTL */
{0x69u, WRITE, 0x5Du, 0x00u}, /* PDMCTL2 */
{0x69u, WRITE, 0x48u, 0x00u}, /* ERRMGMT */
{0x69u, WRITE, 0x4Au, 0x10u}, /* GPIODAT */
{0x69u, WRITE, 0x4Du, 0x00u}, /* GPIOOEN */
{0x69u, WRITE, 0x4Eu, 0x00u}, /* GPIOIEN */
{0x69u, WRITE, 0x50u, 0x00u}, /* PINTEN */
{0x69u, WRITE, 0x51u, 0x00u}, /* PINTINV */
{0x69u, WRITE, 0x52u, 0x00u}, /* PINCFG */
{0x69u, WRITE, 0x20u, 0x00u}, /* TESTMODE */
{0x69u, WRITE, 0x59u, 0x01u}, /* CLK1CFG */
{0x69u, WRITE, 0x5Au, 0x00u}, /* CLK2CFG */
{0x69u, WRITE, 0x60u, 0x00u}, /* UPMASK0 */
{0x69u, WRITE, 0x61u, 0x00u}, /* UPMASK1 */
{0x69u, WRITE, 0x62u, 0x00u}, /* UPMASK2 */
{0x69u, WRITE, 0x63u, 0x00u}, /* UPMASK3 */
{0x69u, WRITE, 0x64u, 0x00u}, /* UPOFFSET */
{0x69u, WRITE, 0x65u, 0x00u}, /* DNMASK0 */
{0x69u, WRITE, 0x66u, 0x00u}, /* DNMASK1 */
{0x69u, WRITE, 0x67u, 0x00u}, /* DNMASK2 */
{0x69u, WRITE, 0x68u, 0x00u}, /* DNMASK3 */
{0x69u, WRITE, 0x69u, 0x00u}, /* DNOFFSET */
{0x69u, WRITE, 0x81u, 0x00u}, /* GPIOD0MSK */
{0x69u, WRITE, 0x82u, 0x00u}, /* GPIOD1MSK */
{0x69u, WRITE, 0x83u, 0x00u}, /* GPIOD2MSK */
{0x69u, WRITE, 0x84u, 0x00u}, /* GPIOD3MSK */
{0x69u, WRITE, 0x85u, 0x00u}, /* GPIOD4MSK */
{0x69u, WRITE, 0x86u, 0x00u}, /* GPIOD5MSK */
{0x69u, WRITE, 0x87u, 0x00u}, /* GPIOD6MSK */
{0x69u, WRITE, 0x88u, 0x00u}, /* GPIOD7MSK */
{0x69u, WRITE, 0x8Au, 0x00u}, /* GPIODINV */
{0x69u, WRITE, 0x80u, 0x00u}, /* GPIODEN */
{0x69u, WRITE, 0x90u, 0x00u}, /* MBOX0CTL */
{0x69u, WRITE, 0x96u, 0x00u}, /* MBOX1CTL */
{0x69u, WRITE, 0x5Cu, 0x00u}, /* SUSCFG */
{0x69u, WRITE, 0x58u, 0x00u}, /* I2SRRSOFFS */
{0x69u, WRITE, 0x57u, 0x00u}, /* I2SRRCTL */
{0x69u, WRITE, 0x2Eu, 0x00u}, /* TXACTL */
{0x69u, WRITE, 0x30u, 0x00u}, /* TXBCTL */
{0x69u, WRITE, 0x1Bu, 0x10u}, /* INTMSK0 */
{0x69u, WRITE, 0x1Cu, 0x00u}, /* INTMSK1 */
{0x69u, WRITE, 0x1Eu, 0x00u}, /* BECCTL */
{0x68u, WRITE, 0x3Fu, 0x00u}, /* I2CCFG */
{0x68u, WRITE, 0x42u, 0x19u}, /* I2SCFG */
{0x68u, WRITE, 0x44u, 0x00u}, /* I2STXOFFSET */
{0x68u, WRITE, 0x45u, 0x00u}, /* I2SRXOFFSET */
{0x68u, WRITE, 0x47u, 0x00u}, /* PDMCTL */
{0x68u, WRITE, 0x5Du, 0x00u}, /* PDMCTL2 */
{0x68u, WRITE, 0x48u, 0x00u}, /* ERRMGMT */
{0x68u, WRITE, 0x4Au, 0x00u}, /* GPIODAT */
{0x68u, WRITE, 0x4Du, 0x00u}, /* GPIOOEN */
{0x68u, WRITE, 0x4Eu, 0x00u}, /* GPIOIEN */
{0x68u, WRITE, 0x50u, 0x00u}, /* PINTEN */
{0x68u, WRITE, 0x51u, 0x00u}, /* PINTINV */
{0x68u, WRITE, 0x52u, 0x00u}, /* PINCFG */
{0x68u, WRITE, 0x20u, 0x00u}, /* TESTMODE */
{0x68u, WRITE, 0x59u, 0x00u}, /* CLK1CFG */
{0x68u, WRITE, 0x5Au, 0x00u}, /* CLK2CFG */
{0x68u, WRITE, 0x81u, 0x00u}, /* GPIOD0MSK */
{0x68u, WRITE, 0x82u, 0x00u}, /* GPIOD1MSK */
{0x68u, WRITE, 0x83u, 0x00u}, /* GPIOD2MSK */
{0x68u, WRITE, 0x84u, 0x00u}, /* GPIOD3MSK */
{0x68u, WRITE, 0x85u, 0x00u}, /* GPIOD4MSK */
{0x68u, WRITE, 0x86u, 0x00u}, /* GPIOD5MSK */
{0x68u, WRITE, 0x87u, 0x00u}, /* GPIOD6MSK */
{0x68u, WRITE, 0x88u, 0x00u}, /* GPIOD7MSK */
{0x68u, WRITE, 0x8Au, 0x00u}, /* GPIODINV */
{0x68u, WRITE, 0x80u, 0x00u}, /* GPIODEN */
{0x68u, WRITE, 0x57u, 0x00u}, /* I2SRRCTL */
{0x68u, WRITE, 0x2Eu, 0x00u}, /* TXACTL */
{0x68u, WRITE, 0x30u, 0x00u}, /* TXBCTL */
{0x68u, WRITE, 0x1Eu, 0x00u}, /* BECCTL */
{0x68u, WRITE, 0x0Du, 0x10u}, /* DNSLOTS */
{0x68u, WRITE, 0x0Eu, 0x10u}, /* UPSLOTS */
{0x68u, WRITE, 0x09u, 0x01u}, /* SWCTL */
{0x68u, WRITE, 0x40u, 0x00u}, /* PLLCTL */
{0x68u, WRITE, 0x01u, 0x80u}, /* NODEADR */
{0x69u, WRITE, 0x40u, 0x00u}, /* PLLCTL */
{0x68u, WRITE, 0x01u, 0x00u}, /* NODEADR */
{0x68u, WRITE, 0x10u, 0x44u}, /* SLOTFMT */
{0x68u, WRITE, 0x11u, 0x03u}, /* DATCTL */
{0x68u, WRITE, 0x56u, 0x00u}, /* I2SRRATE */
{0x68u, WRITE, 0x12u, 0x01u}, /* CONTROL */
};
