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A2B AD2428 TDM issue

1. We use AD2428 TDM format: TDM16, 48K, 32bit, TX0&TX1, RX0&RX1, TX1 for audio recoreding, BCLK=24.576Mhz.  Our TDM PCB routing length is about 200mm.  BCLK and SYNC as a PCB routing group. TXn as a PCB routing group. RXn as a PCB routing group.  All TDM signals PCB routing length are controlled within 100mil.  Each routing group is covered witch GND separately.  PCB routing characteristic impedance is 50 ohm,  Is this PCB routing  ok for TDM16?

2. If I config the TDM timing with sigmal studio as below,  and config the series resistance:  BCLK with 100R,  SYNC with 33R, TX1 with 33R,   A2B can work normally for audio recording with TX1. If I config series resistance:  BCLK with 33R,  SYNC with 33R, TX1 with 33R,  the audio recording is overamplitude and distortion.  The test wave is as below.  Can you explain the reason for this issue?   Why I config DTXn changes on rising edge of BCLK through sigmal studio,  but actual test is  DTXn changes on falling edge? 

Waveform comparison of SOC side, R1,R2,R3 wave marked are normal audio recorded waveform, and C wave marked is audio recorded overamplitude waveform, you can see when overamplitude, the TX1 Data delay to SYNC edge about one BCLK CLK.

3. If  I config the TDM timing with sigmal studio as below, Configure different series resistance respectively:  BCLK with 0R, 33R, 66R, 100R,   SYNC with 0R, 33R,66R,100R,   TX1 with 0R, 33R,66R,100R,   the series resistance of BCLK, SYNC, TX1 is same all the time.   A2B can work normally for audio recording with TX1.  The test wave for 33R is as below.  Why I config DTXn changes on rising edge of BCLK through sigmal studio,  but actual test is  DTXn changes on falling edge?   What about the actual test wave with 33R for BCLK, SYNC, TX1?

 This Figure is described as same polarity of BCLK,  but also described as A2B_I2SCFG.TXBCLKINV ≠ A2B_I2SCFG.RXBCLKINV,  is any error here?

AD2428 side wave(BCLK, SYNC, TX1 series resistance 33R) :

SOC side wave(BCLK, SYNC, TX1 series resistance 33R) :


  • Hi,

    1. From Hardware Point of view, 200mm trace length is not ideal for TDM signals. Since BCLK is sourced from SOC and DTXn is out from A2B, there will be a round trip delay between BCLK generation from SOC and DTX data latching to SOC. For 200mm trace length, it might increase the delay further and results in setup/hold time issues. So, we recommend to use 100mm or less for TDM signal trace length.
    Also, we recommend to do timing analysis to check the issue due to 200mm trace length.
     
    2. We believe over amplitude and distortion referred here is in the Analog Audio signal. As explained in the previous comment, the issue might be due to incorrect latching of data from DTXn signals because of clock skew.
    Could you share the schematics to verify this?
    Also, we are not able to get details since plots are not highlighted for the case (BCLK with 100R). It is not recommended to use different value of resistors for BCLK and DTX/DRX signals as it will create data skew.
    We recommend to use 0-ohm resistor for BCLK, SYNC, TX1 and check for over amplitude/distortion issues.

    Also Please refer to the AD242x Datasheet for I2S timing spec for minimum setup and hold time requirements.

    3.Refer to comment in S.No#1, we don't recommend using different value resistors for BCLK, SYNC and DTX, it will result in data skew.

    Regarding TDM32(for 50MHz operation), we recommend to use same edge for both TX and RX to meet the timing specifications,  it is a typo in manual showing not equal. We will be correcting it in the next version of manual.

    Also please make sure the TDM settings between the HOST DSP and the A2B Master are matching. If there is any mistake in TDM settings, then also it is possible to see data distortion.

    Regards,
    Rajarajan


  • Hi, Rajarajan

    TKS for your replay!

    1. About the PCB routing length of TDM16,  we have an another Project(E28A) with routing length about 100mm,  but also have the same problem.   So the root cause for the problem might have nothing to do with routing length,   of course the setup/hold time we will test to confirm again.

    2. Yes,  over amplitude and distortion referred here is in the Analog Audio signal.  I believe the issue might be due to incorrect latching of data from DTXn signals,  especially the MSB of each slot.    Can you explain why MSB has a significant impact on the amplitude?    Why I config DTXn changes on rising edge of BCLK through sigmal studio,  but actual test is DTXn changes on falling edge for two projects with different PCB routing length?   Maybe the SW configuration have some issue?   Waveform comparison of SOC side, R1,R2,R3 wave marked are normal audio recorded waveform, and C wave marked is audio recorded overamplitude waveform, you can see when overamplitude, the TX1 Data delay to SYNC edge about one BCLK CLK.  

      

     3. We use TDM16 configuration.   When use the different edge for DTXn changing, DRXn sampling through SigmalStudio,  will cause issue.  When use the same edge for DTXn changing, DRXn sampling through SigmalStudio,  it is ok.  I use TDM16 configuration actually , but config the same edge for DTXn changing, DRXn sampling(TDM32 timing) through SigmalStudio,   will it have any issue?      Why I config DTXn changes on rising edge of BCLK through sigmal studio,  but actual test is DTXn changes on falling edge for two projects with different PCB routing length?   Maybe the SW configuration have some issue? 

        

        

  • Hi,

    The Data may be changing on the different edge due to the minimum setup and hold time requirements. Because of the trace length, if those are violated we may see data changing on different edge then which is configured. We have seen similar type of observations for TDM32 with 32 bit slot size, that is why we suggest to use same edge for both sampling and driving in that case to avoid any audio distortion.
     
    Regards,
    Rajarajan