AD2428W pad & master TDM16 sending question

Hi Guys:

     there are two question need your help.

     1、My current ad2428w bottom pad is all grounded, but I see that the data manual is divided into four areas of grounding. Is this design to slow down heat dissipation and facilitate welding?

     2、I recently made the second version of PCB, and then proofed it out, and found that there was a problem with the TDM signal transmitted by ad2428w.  

          Our platform is Qualcomm + ad2428w. the master AD2428W -> output TDM signal to  Qualcomm. I found that the TDM data and the clock were misaligned, and the downstream microphone data had no negative polarity data. It was only solved by adding a 33r resistor BCLK. When it was added to 133r, the waveform changed too much, which was close to a triangular wave. I knew very well that it was our PCB design problem, because there was no problem with the first version. Can you give us some suggestions on the hardware design of tdm16 or tdm32? At present, we want to know the reason to change the next version.

thanks a lot!

Parents
  • 0
    •  Analog Employees 
    on Jul 20, 2021 1:24 PM

    Hi Terry,

    1. i)   Dividing the EPAD into four squares is optional, We have seen even in some of our internal boards single ground pad with adequate    thermal via is sufficient.
      (ii)  Also, we want to confirm the maximum temperature expected for this application. Since AD2428 was intended for Automotive application the temperature range is upto 105ºC
      (iii) If the expected temperature range is less, then there will be additional Margin.
      (iv)  However, we strongly recommend the customer to do actual thermal measurement on their board to arrive at the temperature rise.

    2.Can you please verify the TDM setting between Qualcomm SOC and A2B node whether the driving and sampling edges matches, if possible please share the scope plots of I2S signals.

    Regards,
    Rajarajan

  • Hi RRG:

       Thanks!

       Qualcomm soc  example:

     tdm_quat_tx: qcom,msm-dai-tdm-quat-tx {
      compatible = "qcom,msm-dai-tdm"; 
      qcom,msm-cpudai-tdm-group-id = <37169>;
      qcom,msm-cpudai-tdm-group-num-ports = <5>;
      qcom,msm-cpudai-tdm-group-port-id = <36913 36915 36917
           36919 36927>;
      qcom,msm-cpudai-tdm-lane-mask = /bits/ 16 <5>;
      qcom,msm-cpudai-tdm-clk-rate = <24576000>; // clock fre

       qcom,msm-cpudai-tdm-clk-internal = <1>; // SOC as master

       qcom,msm-cpudai-tdm-sync-mode = <0>; // short sync
      qcom,msm-cpudai-tdm-sync-src = <1>;
      qcom,msm-cpudai-tdm-data-out = <0>;
      qcom,msm-cpudai-tdm-invert-sync = <0>; // normal
      qcom,msm-cpudai-tdm-data-delay = <0>; // Number of bit clocks to delay data with respect to sync edge: 0BIT

     

    32bit is correct. i am considering  the problem is probably in the PCB design, the software was OK on version 1, but the hardware version 2 showed this problem.Some considerations may be needed to guide the PCB design of TDM16.

     

  • 0
    •  Analog Employees 
    on Jul 23, 2021 10:54 AM in reply to terryyuan

    Hi Terry,

    From the waveforms it look like 50-50 FS mode is used, but the setting of A2B are contradicting for the same(Pulse mode). Please make sure the TDM settings are matching between qualcomm SOC and A2B.

    Regards,
    Rajarajan

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