How A2B devices control the ADC peripheral device's START pin at same time?


As we all known, most of ADC devices' interface include START/RESET, SYNC, SCLK and DOUT signals. In a synchronous DAQ system, we must ensure START/RESET, SYNC and SCLK have same phase or timing. 

If an ADC device as an A2B slave peripheral,  SYNC signal timing is possible through adjusting the SYNC offset value, SCLK timing is synchronized because it divided from PLL output which is lock the A2B bus master's BCLK.

How about START/RESET signal? Is there any possible to produce a synchronized "START" pulse in each A2B device's GPIO pin?

If it can, how about the synchronous error?

  • 0
    •  Analog Employees 
    on Jun 23, 2021 4:44 AM

    Hi Minghu,
    Yes, GPIO can be used as START pulse in all the nodes. If GPIO over distance is used between Master and the slave nodes, one of the GPIO input pin is mapped to GPIO output pin of all the slave nodes through a same virtual port, all Slave GPIO’s data will be updated in same superframe with a difference of cable delay in terms of ns.
    Can you give more details about START/reset pulse required for the ADC you are using?

    When this signal is required? Is it at every super frame when data available? It would be helpful to suggest any other method possible.

  • Hi Rajarajan,

    Thank you very much for your quick response.

    START pulse is a trigger signal to start the first ADC's conversion.I am using ADS127L01 from TI, it has a START pin to synchronize the starting point among different ADC ICs. 

    You mentioned that  all the slave nodes through a same virtual port will be updated in same superframe, that's a good news.

    Because SYNC signal timing can be tuned in the step of one SYSCLK period(that is about 20ns, good enough), I'd like to use one flip-flop clocked by SYNC signal and data-in by the virtual port GPIO to reproduce a synchronous version START signal in slave node side. In every SYNC positive edge, START will updated in flip-flop's Q output.

    Host MCU on master node side only need produce low pulse once on the virtual port when it want to re-synchronize all the ADC ICs' conversion timing.

    Do you agree?

    Best regards,   

  • 0
    •  Analog Employees 
    on Jul 1, 2021 7:00 AM in reply to MinghuZhao

    Hi Minghu,

    Yes, looks good. We don’t suspect any problem with the above approach but please make sure it is tested on bench before using it on actual system.