AD2428 Loopback test

Hi Karthik,

Please refer the below attached image on how to loopback the data in the slave transceiver. Host processor can generate the known data pattern and which needs to be received by Master. Through the A2B Bus, the received data slots can be passed to Slave by configuring the Slot configuration register for Downstream. Here, the slave can configure the A2B_I2STEST.BUSLOOPBK bit to loopback the DTX0/1 block data to DRX0/1 blocks as represented in the image. After, the data placed into the DRX0/1 block of slave can be send to Master node via A2B bus in upstream if slot configurations are done. The received data in the Master can be seen in the DTX pins. You can compare the Host Transmit data with Master Tx data to confirm the Slave loopback works.

 
Also please refer the sections "I2S TDM Test Mode (I2S Loopback)" and  "I2S Loopback" in AD242x TRM to find the necessary configuration for Loopback test with A2B transceivers. Pattern generation and loopback test modes are provided for easy validation of I2S/TDM connectivity in master and slave nodes.

Do i need to connect the DTx0 and DRX0 pins physically?
>> The AD242x transceivers supports I2S loopback inside the transceiver.

Still if you have any clarification, please elaborate your expected loopback scenario to test so that I can help better here.

Regards,
Dinesh

HI Dinesh,

Thanks for your input. please find the scenario what we are doing .

Scenario:

Master sends 6 channels of downstream data which shouldn’t be consumed by the slave but should be looped back to the master, hence sending 6 channels of upstream data.

No peripherals are connected to the Master or to the slave.

I2STEST.BUSLOOPBK has been enabled on the slave only

But with the below mentioned configuration we are not able to see any data on the DTX0 pin of the master

We have configured:

Master Slave

DNSLOTS = 0x06 DNSLOTS = 0x06

UPSLOTS = 0x06 UPSLOTS = 0x06

LUPSLOTS = 0

LDNSLOTS = 0x80

DNMASK[0:3] = 0

UPMASK[0:3] = 0

I2SCFG = 0x00 I2SCFG = 0x00

Please suggest the changes that we need to do in the current UPSLOT, DNSLOT and I2SCFG and I2SGCFG register configurations for the slave and master.

Hi Karthik,

Regarding, "Master sends 6 channels of downstream data which shouldn’t be consumed by the slave but should be looped back to the master, hence sending 6 channels of upstream data."
>> The slave should consume the data from the downstream of the Master in order to Transmit out in DTX pins or Loopback internally in the TDM/I2S block.

Regarding,"Please suggest the changes that we need to do in the current UPSLOT, DNSLOT and I2SCFG and I2SGCFG register configurations for the slave and master."
>> Please find the below required configurations for the A2B Slave Bus Loopback test scenario as shown in the earlier attached image.

The below AD242x Slave Node0 configuration is to consume the 6 Channels of data from the downstream and send the 6 channels of  data in upstream for your scenario.

"LDNSLOTS"=0x80
"LUPSLOTS" =0x06  
"I2SGCFG"   =0xE4
"I2SCFG"      =0x19
"DNMASK0"=0x3F
"I2STEST"    =0x10

The below AD242x Master Node configuration is to consume the 6 Channels of data from the upstream and send the 6 channels of  data in downstream for your scenario.

AD242x Master Node0
"I2SCFG"   =0x19
"DNSLOTS"=0x06
"UPSLOTS" =0x06
"SLOTFMT"=0x44
"DATCTL"=0x03
"I2SGCFG"=0x24

If you use the above configuration in the Discovery flow (which you are following to discover and initialize the nodes in your A2B system), you will find observation of slave data LOOPACK in the DTX of the Master node from its upstream, once A2B system Discovery is done.

Please make sure the input data patterns are provided in DRX0 of the Master from any Source/HOST, so that you can expect the same from the DTX of the master.

Also I would suggest you to please refer the below link to understand How the TDM channel mapped to slots on the A2B bus.
ez.analog.com/.../how-is-the-tdm-channel-mapped-to-slots-on-the-a2b-bus

Regards,
Dinesh