When using ADAU1452 on AD2428WD1BZ evaluation board as audio Host, how should I configure TDM settings?

When using ADAU1452 on AD2428WD1BZ evaluation board as audio Host, how should I configure TDM settings?

  • +1
    •  Analog Employees 
    on Sep 2, 2020 4:41 PM 7 months ago

    To understand the co-relation settings between A2B and ADAU1452 when using ADAU1452 on AD2428WD1BZ evaluation board as audio Host, please find the below images which illustrates on how ADAU1452 Serial Port settings are co-related with A2B DTX/DRX settings on each other.

    On AD2428WD1BZ, Serial OUT0 and Serial IN0 blocks are connected to I2S/TDM interface of A2B node. Therefore, it is required to match the settings of these serial ports with I2S/TDM interface settings of A2B transceiver.

    - When LRCLK type of ADAU1452 is 50/50 duty cycle clock, change the corresponding Sync mode in master A2B node properties as well to "50% Duty cycle". When LRCLK type is "Pulse", change the corresponding Sync mode in master A2B node properties to "Pulse".

    - When LRCLK Polarity of ADAU1452 is "Positive Polarity", change the "Sync Polarity" setting in master A2B mode properties to "Rising edge". When LRCLK Polarity of ADAU1452 is "Negative Polarity", change the "Sync Polarity" setting in master A2B mode properties to "Falling edge"

    - When BCLK Polarity of ADAU1452 is Positive polarity, that means, data should change on Rising edges. In the A2B master node properties, set the DRXn Sampling BCLK to "Falling edge". So that A2B node would sample DRX pins on falling edge, because ADAU1452 drives on Rising edge Similarly, set the DTXn change BCLK to "Rising edge". So that A2B node would drive the DTX pins on Rising edges, as expected by ADAU1452.

    - When BCLK Polarity is Negative polarity, that means, data should change on Falling edges. In the A2B master node properties, set the DRXn Sampling BCLK to "Rising edge". So that A2B node would sample DRX pins on rising edge, because ADAU1452 drives on falling edges Similarly, set the DTXn change BCLK to "Falling edge". So that A2B node would drive the DTX pins on falling edges, as expected by ADAU1452.

    -Based on Data Format (defined by "MSB position" setting): if data format is Left justified in ADAU1452, Disable the Early Sync option in A2B master node properties If data format is I2S (BCLK delay by 1), then enable the Early Sync option.

    -Set the TDM mode same in both ADAU1452 settings and A2B master node properties

    Please note that direction of BCLK and SYNC signals of any ADAU1452 Serial Ports (IN/OUT) can be any. i.e. Serial port (IN/OUT) blocks can generate BCLK & LRCLK signals (clock master) or it can import clocks from its pins (clock slave).

    On AD2428WD1BZ board, the Serial IN0 and Serial OUT0 blocks are connected to A2B transceiver as shown below:

    For Instance, if we connect BCLK_OUT0 and BCLK_IN0 signals externally; and also LRCLK_OUT0 and LRCLK_IN0 signals, then any block (Serial OUT0 or Serial IN0) can be configured as clock Master and other block should be configured as clock slave (taking BCLK and LRCLK from its pins). For example, Serial IN0 block can be configured with option “Slave from CLK domain 0” to instruct serial port to take clocks from it’s pin BCLK_IN0 and LRCLK_IN0.

    If the BCLK signals and LRCLK signals of OUT0 and IN0 blocks are not connected externally (due to 3-way jumper issue), then both blocks can be configured as clock master. Both the blocks would generate synchronous clocks, therefore A2B clocks can be connected to clocks of either block and other block clocks can be left unconnected.

    If both primary and secondary lines are used DTX0/1 and DRX0/1, then Serial OUT1 and Serial IN0 blocks should be configured with identical settings.

    Also, if two data lines (DTX1 & DRX1) are used for transmission and reception in A2B nodes, Serial IN1 needs to follow the same settings as Serial IN0; and Serial OUT1 needs to follow the same settings as Serial OUT0.

    The serial IN1 blocks can take clocks from serial IN0 block and serial OUT1 blocks can take clocks from serial OUT0 block.

    Or serial IN1/OUT1 blocks can be configured as clock masters same as serial IN0/OUT0 blocks.

    In the AD2428WD1BZ Evaluation board schematic, the connection of AD242x and ADAU1452 signals BCLK and LRCLK as follows. Using Jumper 5 we can connect the BCLK_OUT0 or BCLK_IN0 signal of ADAU1452 to A2B BCLK. Similarly, Jumper 6 can connect LRCLK_OUT0 or LRCLK_IN0 signal of ADAU1452 to A2B SYNC.