Andreas
- Status Level:
-
Analog Employee (124 points)
- Member Since:
- Apr 22, 2009
- Last Logged In:
- Mar 19, 2010 6:55 AM
- Company:
- Analog Devices
Recent Activity
BF561: Edge Sensitive Interrupt and read from FIOx_FLAG_D register
"Hi, you need to switch to level sensitive, read the value and switch back again. Regards Andreas" in Blackfin Processors - 4 replies |
2 days ago |
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BF561: Edge Sensitive Interrupt and read from FIOx_FLAG_D register
"Hello, is this a question or an observation? In either case here's the explanation: http://ez.analog.com/message/1379#1379 Regards " in Blackfin Processors - 4 replies |
2 days ago |
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SPI master boot failure at higher baud rate
"Hello, I would suggest that we close the discussion here, because... I've sent a hardware and my complete project to ADI for diagnosis. I" in Blackfin Processors - 11 replies |
2 days ago |
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UART on BF527
"Hi, sorry for the two months delayed response. I just forgot about your latest response and questions. You can emulate CTS / RTS with G" in Blackfin Processors - 5 replies |
2 days ago |
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Boot Stream Size limitation?
"Hi, do you know that VisualDSP++ provides init code examples ( \Blackfin\ldr\init_code )? Regards Andreas" in Blackfin Processors - 7 replies |
2 days ago |
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SPI master boot failure at higher baud rate
"Hi, can you dump the content of the Boot ROMs pLogBuffer at address 0xFFB04000 after the booting process stops? Each content of the log" in Blackfin Processors - 11 replies |
2 days ago |
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Problem with Locked CPLBs
"Hi, how is your CPLB table created? Are you using the CRT? Or VDK? Each CPLB entry can be locked individually and actually only the ones" in Blackfin Processors - 2 replies |
2 days ago |
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[BF538, SPI Slave Rx, DMA] What did I wrong?
"Hi, I suggest that you read the SPI chapter in the ADSP-BF537 HRM. This document contains very detailed flow charts about all the require" in Blackfin Processors - 3 replies |
2 days ago |
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Boot from internal SPI Flash on BF518F
"Hi, please check the official init_code examples provided by VisualDSP++ ( Blackfin\ldr\ ). You're PLL accesses don't follow any guidel" in Blackfin Processors - 3 replies |
5 days ago |