Hi Windy,

It is not clear what information you are looking for. Are you looking for information on shared memory support for 21368. If so you can fnd the information in the external port chapter of 21367/8/9 HRM available at the following link.

http://www.analog.com/static/imported-files/processor_manuals/34347149857507ADSP_21368_HRM.pdf

Please note that shared memory support is available only for external parallel port of the DSP. It is not available for the SPI port if that is what you are looking for.

Thanks,

Divya

Hi Windy,

If you are planning to SPI Boot both the devices from the same flash this is not possible assuming you are not having any timing relationship for powering up the devices . Also note that there is no intrinsic shared memory support for SPI on the DSP. That being said if your system is such a way that only one DSP device accesses the SPI flash device at a time you could OR the SPI chip select from both the devices using an external OR gate and make sure in software only one device is accessing the SPI flash at a time by using GPIO Flags for handshaking.

Hope this answers your question. Please let me know if you need any further information.

Thanks,

Divya

Hi Windy,

>>Maybe we don't need 2 DSP access the SPI Flash at the same time , about the leading , main DSP set as

>>SPI Master Boot method , and daughter DSP set as SPI Slave Boot method ; and SPI Flash chip select

>>connect with main DSP FLAG0' pin , FLAG0, FLAG1 connected with the not gate then leading the SPIDS

>>pin of daughter DSP . leading the main DSP trought SIP Flash while power up reset . and put up the

>>SPIDS pin of DSP meanwhile , so this can make the DSP to release SPI boot ,

Well I don’t see a problem with this as you are talking  to the SPI Flash while the other DSP is in slave mode not driving the SPI lines and the SPIDS is not selected.

>>and leading the daughter DSP after the main DSP leading completed . please advise if this method can >>be done ?

By leading the daughter DSP  if you mean to change the boot config pins to master boot to boot from flash it is not possible as boot config pins have to be valid before reset pin is asserted. If you plan to use the slave boot mode you would need a host or an other processor to provide the SPICLK  and data for slave booting and cannot boot from flash.

Hope this clarifies.

Thanks,

Divya

Hi Windy,

>>Thanks , we won't make the daughter DSP to read the needful date for root from SPI Flash directly , but providing daughter DSP SPICLK and date after >>the master DSP root , just physical connect 2 DSP' SPI bus and SCLK, MISO, MOSI of SPI Flash together , and control the chip select signal >>additionally , can this be approched ?

As you intend to have single master and two slaves in your system and are planning to access the slaves one at a time using the flag pins, I don't see any issues with it.

Thanks,

Divya

Hi,

Just to sum up your system ,you are planning to have one DSP in SPI master boot mode and the other DSP in SPI slave boot mode. The master DSP will be driving the SPI signals to the flash and the second DSPs chip select is not enabled on reset. If this is the case then you shouldn't have any race conditions as only one device is driving the SPI signals at a time.

Thanks,

Divya