In a linux-related thread
where the issue is related to only using the sport SECONDARY channel for codec connection due to desired overall pin assignments.
It has been pointed out that the SPORT will not work as desired when a TX or RX pin of the PRIMARY channel is individually assigned as GPIO-function.
At this time I realize that this limitation could apply to other SPORT pins (clock & frame strobe) as well.
So, if I only need one single clock, because the SPORT is used as master, I'd arbitrarily like to define either TFS or RFS resp. TXCLK or RXCLK as a GPIO, in order to utilize the chip utmost. Well, given the limitation as outlined about, I'm afraid that similar limitations occur related to these pins...
Thanks for raising this up. We are aware of some similar issues and I believe our internal team is working on it.
As per my understanding of SPORT module pins:
- When SPORT is operating in internal clock mode (ICLK=1) then we cannot use SPORT_CLK pin in GPIO/other function mode. The corresponding pin must be configured as SPORT_CLK pin. (If we use SPORT_CLK pin as GPIO, signal on SPORT Data pin gates according to status of that GPIO pin)
- There is no such limitation on SPORT_FS pin, when SPORT is operating in internal FS mode (IFS=1).
- As Primary Transmit Data pin is enabled by default (with TSPEN bit is set), we must configure DTPRI Data pin in PORT mux.
- Secondary Data pin can be disabled in PORT Mux.
This is what my understanding is. If you can contact to private support channel, I will confirm these from our internal team.
But by looking at your description, I think you are facing some problems with SPORT_FS and SPORT_DRPRI pins as well (which I think, should not). If you can provide more information about these problem, then that would be helpful.
Thanks for contacting Processor Support.
Your query was :
I want to use any of the two SPORT interfaces in master mode, while the attached audio codec is in slave mode. Most audio codecs have 4 pins for PCM. So 4 pins SPORT should fit, e.g. DTxPRI, DRxPRI, TXCLKx, TFSx. As such, RFSx & RSCLKx are not needed. However: the datasheet supplies no information whether these pins can be muxed as GPIO without affecting SPORT operation. It is my intention to optimize pin resources.
Sport Tx and Sport Rx are independent modules in normal Sport operation (Non mulichannel mode). You cannot directly use DRxPRI without RFSx and RSCLKx.
Two options are -
1) Use external framesync and clock for Sport Rx, connect TFS to RFS and TSCLK to RSCLK. But here you cannot use RFSx and RSCLKx as GPIO, because you still have to connect TFS to RFS and TSCLK to RSCLK.
2) Use internal framesync and clock for Sport Rx. But here the data received on DRxPRI will not be synchronized with TSCLK. As mentioned by Prashant, when RSCLK in internal mode you cannot use RSCLKx pin as GPIO.