Hi
I am using AD8054 in sallen key topology for designing a 6th pole bessel filter. The cut-off frequency of the designed Bessel filter is 14MHz.
We have simulated the circuit using Multisim and observed a cutoff of 14Mhz. However the same circuit on the PCB we get a cutoff of 7Mhz.
I am attaching the schematics of the same, can anybody clarify as to why a cut-off of 7Mhz is observed?
What should i do to achive a cut off of 14Mhz, kindly advise.
Regards
SRV
SRV,
The caps on the input pin to ground are 10 pF. The input capacitance is typically 1.5 pF. I don't
know if the spice model models this or not. I would double the size of your caps and cut the resistor
values in half. You also have to put in some parasitic caps to model the pc board stray capacitances.
It's also difficult to get good performance using quads for active filters. You have lots of passives
around a quad so you can have cross talk between different traces. I would use two duals or three
singles.
The equations for active filters usually assume the gbw for the op amps is infinite. To make the
equations come close, you need a gbw at least 50-100 times the Fc*Q product. So the AD8054
does not meet this.
Finally, check out:
http://www.eetimes.com/design/analog-design/4210663/Op-amps--to-dual-or-not-to-dual---Part-1-of-2-
http://www.eetimes.com/design/analog-design/4210881/Op-amps--to-dual-or-not-to-dual---Part-2-of-2-
Harry
Harryh,
We did double the capacitor values and reduce the resistor values. This have improved the cut off frequency. Thanks for the feed back.
Regards
SRV
Hi Harryh,
This has actually improved our 3dB frequency, however i wanted to know the relation between " double the size of your caps and cut the resistor values in half " to 3dB frequency. Can you plz let me know the same.
Your help is highly appreciated.
Regards
Shilpa
SRV,
Active filters are a complicated subject and there are dozens of books on them. For most topologies,
F and Q are a function of several resistors and capacitors, so you will see some function of R1*C1*R2*C2.
So if you decrease R by two times and increase C by two times, the product remains the same.
If you make the resistors too large, the thermal noise of the resistors degrade your SNR, but if you
make the resistors too small, the op amp can't drive them.
For your schematic, the 845 ohm, for example, in combination with the 10 pF capacitor, has a pole
at 18.7 MHz. However, the AD8045 has an input capacitance of about 1.5pF, which is in parallel
with the 10 pF, so that is a 15% error in your equations. So that is why I said decrease the resistors
and increase the caps. PC board stray capacitance can be a few picofarads also.
If you have two blocks with a -3 dB point at xx MHz, when you cascade them, you will have
-6dB at that frequency. So you may want to deliberately set your equations for a higher
frequency, say 20 MHz, and calculate the R and C values.
You may want to consider a passive L-C filter network with a buffer on input and output.
Harry
