Hello Javier
For your question 1. The robustness trade-off with cost (i.e. components), therefore for minimum components! you need to factor this in.
There are numerous way in resolving your design. This would required more than just a few thread in EZ. We need to take this off-line, Where we can get more info, in order to propose some architectures for your consideration. Things that need to be consider is your requirement and specifications in order to implement the architecture. You can contact me by email thru CAC Europe. I believe you may also have my answers to (Q3) thru our ADI representative. If not please see (3) below for your answer. For (Q2) the query was too brief, can you elaborate, again you can reply to my answer thru the CAC Europe (SR#: 1134516).
Answer to question 3:
=> There is a typo in fig2.
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(i) wrt TC (Thermocouple) i.e. in the sub diagram/box, It should ideally read (from left to right) as Jx-1, Jx-2, Jx-3, Jx-4. Where the x is either 'ALL' channel one i.e. (1). Or, x is either 'ALL' channel two i.e. (2). Hence you can in effect have up-to two TC (one per channel). This should clear up everything. I have cc the circuit note (CN) team leader, where they will factor this notification for the next doc revision/update, please accept our apologies.
Further to this TC connection, below is my decoding of the CN schematics for the TC (thermocouple) path/configuration to the ADC
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This is best describe and refer in-conjunction with the full schematics by means of tracing the signal path to the ADC, see the circuit note (CN0209)companion documentation, EVAL-CN0209-SDPZ-SCH- RevB.pdf.
For TC (in fig 2), For each channel this can be connected to the ADC thru the ADG switches. Note, this can be (a) either (b) or both, be connect thru the switch (ADG1414/ADG442)!. For control, please see each respective ADG datasheet for more detail.
IF say your connection is thru ADG1414 you need to program these switches. Again this can be refer to the companion schematics (isolator switch, blackfin SDP) and the software.
If it's configured appropriately (all the way to and including) the ADC (AD7193). Then the input to the ADC i.e. => AIN3 (is singled-end), while (thru ADG442) the ADC port (AIN1 + AIN2), (AIN5 + AIN6) are differential.
Hope this helps, in which way and what ends up to the ADC.
Regards,
Ching
Hello Ching, first of all, thaks for your answer. I don´t know how to answer thru CAC Europe.
Hi Javier
(1) I presume your 3 vias, is the connector header pins you are talking about. If this is correct then several scenario exists (a) do you want to maintain consistency as the CN' design but with 8 channels, than the current 2. (b) use one ADC as its 8 channels (but this restricted to single end-ed. (c) a mix and match.
For (a) it’s the simplest, hence i.e. is just some duplication of the switches and 3 extra adc. Advantages can have 4 simultaneous ADC running.
For (b) need some thinking if do-able for one x 8 channel ADC. you need to provide more feedback info for requirements. see below
For (c) needs more feedback info for requirements . see below.
Can you advise which preference (i.e. single end-ed, differential) and what's do-able in meeting your requirements.
for (2) is easier to answer with a phone call. Please provided.
for (3) i thought this was answered previously. else please elaborate. Hence it's Jx-2: and Jx-3:
Can you let us know if you have the EVAL-CN0209-SDPZ, where you can do some initial evaluation for your requirement specification.
Regards,
Ching
Hi Ching.
First of all, the initial requeriments of my project:
- 8 universal analog inputs (RTD, TC, 4-20, Voltage). 3 header pins.
- Each channel can be configurated independently for RTD, TC ... measurement mode. Another choice if this option complicates the design (cost & component number (PCB size)), 2 blocks (4+4 inputs) and can configurated each block for each measurement mode.
- The sample rate is not a critical factor.
- This is controlled for a 32 bits ARM Cortex kinetis, communications Ethernet, CAN and RS-485. It´ll be a web based application.
I´ll configure each analog input (with switches and analog multiplexers, jumpers no allowed), with a software through communications, and monitoring too.
Another question:
How the third wire RTD is compensated? The circuit does not connect the wire to the analog input....
What would be the equation to calculate the resistance?
Thanks again, Ching.
Regards.
Hi Javier
I think to support you better.
(a) Can you get hold/purchase one of the eval-board for testing and evaluation.
(b) Have a look at the attached files
(c) To support you further, do you know of any ADI representative or ADI (authorised) distributer (FAE) in your area. where they can assist and liaison with. As thru EZ would be difficult to go thru all the scenarios if you are not familar with the CN designs.
Regards,
Ching
