DSP Support Forum : Popular Threads - All Communities

Sensor Communication Problems

analog@sgaur.hosted.jivesoftware.com — Tue, 03 Nov 2009 05:53:54 GMT

Hi guys!

I have a problem with my MT9V135 sensor. Apparently, when I run the program for interfacing Micron sensors to the BF537 EZ-Kit Lite, the sensor does not recognize the slave address or TWI address that the program designates; an "Address Not Acknowledge" (ANAK) bit occurs in the

TWI_MASTER_STAT register. As a result, the master mode transmit operation does not push through; and register values are not programmed into the sensor registers. Thus, the sensor does not operate.

Although, I've considered other possible TWI addresses that are specified on the sensor datasheet and the configuration settings for MI354 revision 2 sensors, the problem still persists leaving me with no choice but to ask help from you guys. I just would like to ask two questions: (1) What are the possible problems that make the sensor 'not acknowledge' the TWI address?; and (2) Do you have data for MI354 revision 4 sensor configuration settings? Again, any help will do and will be greatly appreciated.

Regards,

Allan

Need a code example of slave spi-dma for 21262

analog@sgaur.hosted.jivesoftware.com — Mon, 07 Sep 2009 14:25:28 GMT

I need a code example of SLAVE SPI-DMA for ADSP-21262 (in C).

In the examples supplied with the VisualDSP installation disk, there are only Master examples.

Bootloading Blackfin BF537 with VisualDSP

analog@sgaur.hosted.jivesoftware.com — Thu, 19 Nov 2009 16:15:39 GMT

Hi!

I'm starting to work with DSPs. I have a EZ-KIT with the BF537 on it. I can debug it using the integrated tools, no problem. My problem is, that I should use the Bootloader to get the code on it. I tried to change the preferences of the Project, but I have problems to bootload the code.

Can anyone give me some hints how to do it? Everytime I click on "Load" he want's to connect zu the integrated flash loader, and does not use the UART bootloader. What am I doing wrong?

Sorry for my bad english and many thanks for help.

Regards,

Andi

Processor halts while starting "Run"

analog@sgaur.hosted.jivesoftware.com — Tue, 17 Nov 2009 09:54:40 GMT

Hi,

I am getting a strange problem from one of BF537 based boards. I am able to connect the VDSP to the board properly via HPUSB ICE. The program also loads properly on the board. However most of the time when I run some program on the board then it gives following errors (screenshots attached with message). And the program does not run anymore for that particular “run”. Then after restarting the board several times the program “may” run, or may not run.

Please note that this board was working perfectly all right, and this problem has arisen all of a sudden from nowhere. The same program also runs fine on other boards. Does this mean that the processor on that particular board has gone faulty? Is there any solution to this problem?

Best Regards,

Asif Habib

Implementation of FIR accelerator

analog@sgaur.hosted.jivesoftware.com — Wed, 11 Nov 2009 16:10:55 GMT

Hi,

I use the SHARC 21469 and I would like to use the IIR and FIR accelerator units for processing audio data.

I found an IIR Accelerator Talkthrough example in the forum posted by Mitesh Moonat which works fine.

I tried to modify it to use the FIR accelerator, but it does not work properly and I don't know why.

Perhaps anyone has a working code example or you can take look at my code which is attached to the posting.

Best Regards,

Marc

key shift

analog@sgaur.hosted.jivesoftware.com — Mon, 02 Nov 2009 03:39:48 GMT

Hi Sir ,

Please advise how to do the key shift ? thanks .

Best regards,

Windy

Supply on ADSP21371 EZ-KIT

analog@sgaur.hosted.jivesoftware.com — Thu, 12 Nov 2009 12:07:31 GMT

Hi to all

I was looking the EZ-KIT schematic. About the dual supply for core and I/O(VDDINT, VDDEXT) thelast pin of Vddint31 is connected to Vcc trough a rezistor. Why is that? the sam is for VDDOI19?

BF518F Kit Lite Related

analog@sgaur.hosted.jivesoftware.com — Wed, 18 Nov 2009 11:58:52 GMT

Can the Blackfin Landscape EZ Extender be used with BF518 Kit Lite also. In the information related to LCD extender, its been mentioned as

Blackfin Landscape LCD EZ-Extender for the ADSP-BF526, ADSP-BF537, ADSP-BF538, and ADSP-BF548 EZ-KIT Lites.

But in the Blackfin evaluation kits page, Blackfin Landscape LCD EZ-Extender is mentioned under BF518 also. Please clarify.

Interfacing SDRAM to ADSP21371

analog@sgaur.hosted.jivesoftware.com — Thu, 22 Oct 2009 11:43:36 GMT

Hi, to all

I saw the ADSP- 21371 EZ KIT Lite manual. I don`t understand the connection of the SDRAM memory. Why the DQM0 - DQM3 are tied trough rezistors?And the BA0 , BA1 to ADDR17/ ADDR18?

Null pointer without SDRAM

analog@sgaur.hosted.jivesoftware.com — Tue, 17 Nov 2009 20:44:28 GMT

Hello,

when using the Blackfin with SDRAM, a pointer to address 0 automatically reads 0, which is very practical for null pointer operation. But if no SDRAM is connected, this function is lost. Is there any (tricky) facilitiy to make the bus interface return 0 when a read access is made to the SDRAM address range, but no SDRAM is present?

Thank you in advance for an answer

BF548 Audio signal processing (AD1980 Callback)

analog@sgaur.hosted.jivesoftware.com — Thu, 30 Jul 2009 11:40:03 GMT

Hi,

I'm currently trying to extract audio input data, perform some signal processing, and output something at the end. (Much like the talkthrough on the 533 boards).

I have been using the audio loopback project to attempt this, and for starters, I've tried something very simple: Set all left audio out to zero. (Just to make sure I am actually able to manipulate the data somehow).

In regards to the code, this is what I've done:

/* copy the source (ADC) data to DAC channels */
 for (i = 0;i < (BUFFER_SIZE_PER_CHANNEL * NUM_ADC_CHANNELS); i++)
 {
 /* copy ADC left channel data to PCM out Left */
 *(pDest+(NUM_DAC_CHANNELS*i)) = 0;
 /* copy ADC right channel data to PCM out right */
 *(pDest+1+(NUM_DAC_CHANNELS*i)) = *(pSrc+1+(NUM_ADC_CHANNELS*i));

However, this does not silence the left output at all. I am very confused, am I doing something wrong? Or have I modified the whole thing incorrectly?

I've also noticed that after I press PB4 (to terminate the program), it says "Done!", but audio is still coming in and going out.

Other than what I've written above, I have not changed the program.

I realise it is only a basic operation I am trying to achieve at the moment, but I want to take it one step at a time. It will get much more difficult in the future (planning to write functions which will process a 2 second audio input, and analyse the data, to detect speech), so if you guys could help me get over this hurdle, that'd be great.

Cheers,

Additional information: Using VisualDSP+++ V5 (with update 6 applied).

File edited is Audio_Loopback.c

Codec: ad1980

adi_flag service and ADI_FLAG_TRIGGER_BOTH_EDGES event

analog@sgaur.hosted.jivesoftware.com — Tue, 17 Nov 2009 15:40:19 GMT

I read the VisualDSP++ 5.0 Device Drivers and System Services Manual for Blackfin processor and I tried to write a simple program that installs a callback on ADI_FLAG_PF8 ADI_FLAG_TRIGGER_BOTH_EDGES event.

The problem is that the callback only returns the ADI_FLAG_EVENT_CALLBACK event, both for rising and falling event.

I need to know if the callback has been invoked by a rising edge or a falling adge, but I don't know what to do, so I thought reading the ADI_FLAG_PF8 physical level (not logical one) inside the callback. I'm not completely satisfied about this way, but I don't have other ideas..

If I understood the documentation, the adi_flag_Sense() function returns the logical level, and as a matter of fact I noticed that when I use it inside the callback it always returns TRUE.

I explicitly read the port IO register (*pPORTFIO & PF8) but it always returns TRUE, even if the PF8 pin is physically LOW!!!

Could someone help me?

PS: using BF527 and VisualDSP++ 5.0 Update 6

Thanks in advance

Messaggio modificato da vix

Remove the NAND support from Shell_Browser

analog@sgaur.hosted.jivesoftware.com — Tue, 17 Nov 2009 10:53:39 GMT

Hello,

I am getting stucked with a problem using the shell_browser example.

We have designed a custom card that is based on the BF-526 EZ-KIT, and it has no NAND Flash on it. We use the shell_browser code example to access the USB Flash storage device. I try to remove the NAND PID driver by removing the line

{ ADI_FSS_CMD_ADD_DRIVER, (void*)&ADI_NAND_Def },

in the file InitFileSystem.c, but this hangs up the code.

Has anyone an idea (is there anything else to modify ?)

Thank you for your time !

VDK History view

analog@sgaur.hosted.jivesoftware.com — Thu, 19 Nov 2009 12:40:47 GMT

Hi,

I've a problem with one thread in my VDK application. After thread ends my app become instable.

If I take a look in the VDK history I found an event called "Max Stack Used".

What is ist? The Threads StackSize is big enough...

any ideas?

Thanks

So how about all this programming the host microcontroller stuff, anyhow?

analog@sgaur.hosted.jivesoftware.com — Tue, 17 Nov 2009 17:01:48 GMT

Alright, i'm not Bob Pease....

So I'm new to DSP and I've got the AD1940 EVK and written (drawn) a lovely program in Sigma Studio.

I want to get that code and stuff it into a microcontroller to boot the DSP in the target application.

What do I do? Am I right in thinking i'll need to include xxx_IC_1.h into my microcontroller source, and then write my own functions for all the #defines in SigmaStudioFW.h? Or is there more to it - more files to include maybe? Are there any functions or libraries i'm missing?

What about safeload writes? I can see SIGMA_WRITE_REGISTER_BLOCK() and SIGMA_WRITE_REGISTER() inside SigmaStudioFW.h. Do i need to write functions to write via the safeload registers for run-time parameter updates? Also, what is SIGMA_SET_REGSITER_FIELD ?

Any example C files greatly appreciated - target application controlled by PIC16/18 by the way.

Thanks in advance, sorry about all the questions - it's a lot to get one's head around for a newbie.

Lewis.

Ethernet failing after changing boot mode

analog@sgaur.hosted.jivesoftware.com — Fri, 23 Oct 2009 04:54:39 GMT

We are using ethernet application that was running on Boot mode -000 (Boot from external rom), now we changed the boot mode to - 001 (Boot from external ROM via internal ROM)) because we were getting core fault detection. Now the core fault detection has gone but ethernet error has come.

The error we are getting is

PHY Controller has failed and the board needs power cycled
Failed to initialize system

Lost my CD

analog@sgaur.hosted.jivesoftware.com — Thu, 12 Nov 2009 19:52:25 GMT

Hello!

I have a ADDS-21535-EZLITE board, but I have lost my cd with the VisualDSP++ software.

I have a serial for what I think is version 4. Is there a way to download the software?

Thanks

Bayer pattern convertion

analog@sgaur.hosted.jivesoftware.com — Wed, 08 Jul 2009 07:42:48 GMT

ADI Support,

is there any for the BF561 optimized routine in assembler or ‘C’ routine that converts a Bayer Patter from a CMOS Sensor e.g. Micron MT9V024 into RGB format.

I could not find any optimized routine for BF561. My adapted ‘C’ source code from a PC routine needs about 75% of performance from the Core A when running on the DSP and this is much too much. The routine is very small and code runs from L1 memory. The raw bayer image from sensor is in L3 memory.

A value of 15% of Core ‘A’ performance usage would be the target.

Can you help us in this case getting an optimized routine converting Bayer Patter to RGB24 Bit for the DSP BF561!!!

Thanks

Tommy

SPI Clock dynamic - BF561

analog@sgaur.hosted.jivesoftware.com — Tue, 27 Oct 2009 05:27:54 GMT

Dear Sir ,

We configured SPI of BF561 to drive an ADC , the settings of SPI registers are as below :

1.SPI_BAUD = 0x0002

2.SPI_CTL = 0x5521

All directions controls are taken care , and we are getting all the required handshake /signal also ,but only problem is the change in SPI clock frequency , it will be 10.4 Mhz intially and then while debugging when we halt and again start , the fequency gets adjusted back to 25 Mhz as per our requirement , the current observed by us were around 170mA @ 10.4Mhz and 350mA @25Mhz respectively.

Our crystal is @ 25Mhz and we are multiplying this with 24 to obtain 600Mhz and our system clock is 600Mhz/6 = 100 Mhz

Please comment on the same .

System Services Library BF534 (BRAEMAR)

analog@sgaur.hosted.jivesoftware.com — Tue, 10 Nov 2009 05:34:13 GMT

I am using the BF534 device and the SSL.

I am trying to configure a callback on rising edge on pin PH12.

I assume that the peripheral ID is ADI_INT_DMA1_ETHERNET_RX_PORTH_A

Q1 Is that the correct Perihperal ID to use? (How could it ever differ?)

My code fragment(without error checking, for clarity):
adi_flag_Open (ADI_FLAG_PH12);
adi_flag_SetDirection(ADI_FLAG_PH12, ADI_FLAG_DIRECTION_INPUT);

    /* Now use the input as an interrupt source */
    adi_flag_InstallCallback(                                            // installs a callback for a flag
        ADI_FLAG_PH12,                                                // ADI_FLAG_ID            FlagID,             // flag ID
        ADI_INT_DMA1_ETHERNET_RX_PORTH_A,         // ADI_INT_PERIPHERAL_ID PeripheralID,       // peripheral ID
        ADI_FLAG_TRIGGER_RISING_EDGE,                   // ADI_FLAG_TRIGGER       Trigger,            // trigger
        TRUE,                                                                 // u32                    WakeupFlag,         // wakeup flag (TRUE/FALSE) from sleep?
        (void *)0x1234,                                                    // void                  *ClientHandle,       // client handle argument passed in callbacks
        adi_dcb_ManagerHandle,                                   // ADI_DCB_HANDLE         DCBHandle,          // deferred callback service handle
        dist_CallbackFunction                                        // ADI_DCB_CALLBACK_FN    ClientCallback      // client callback function
    );

The result is that the library adi_flag.c has an interrupt handler FlagHandler()

that calls adi_flag_GetInterruptMask() that tries to establish if the bit is enabled

in the mask register. However, it tests "PeripheralID == ADI_INT_PORTFG_A"

and if false, chooses mask B.

Q 2 Surely it should be like:

    if (PeripheralID == ADI_INT_PORTFG_A || PeripheralID == ADI_INT_DMA1_ETHERNET_RX_PORTH_A) {
        pRegister = pPort->MaskAData;   // Ports F G & H - Mask A
    } else {
        pRegister = pPort->MaskBData;   // Ports               - Mask B
    }

in order to handle the Port H pins too?

The modified version seem to work as expected. Is this the correct fix?

Regards,

Colin.

Release vs Debug

analog@sgaur.hosted.jivesoftware.com — Wed, 18 Nov 2009 19:15:49 GMT

Is there a global define provided by the IDDE to identify Release and Debug modes? I need to configure the PLL/SDRAM init differently for stand-alone vs emulator modes.

Running exported makefile under Windows

analog@sgaur.hosted.jivesoftware.com — Thu, 19 Nov 2009 21:29:03 GMT

I can compile my code in VisualDSP++ but when I exported my makefile using "Project Options->Export Makefile..." and tried to run it under a Windows XP command prompt (i.e, cmd.exe) I get the following error:

set PATH=C:\Program Files\Analog Devices\VisualDSP 5.0;%PATH%

gmake-378 -f tmm_export.mak tmm_Debug

"Linking..."

'C:/Program\' is not recognized as an internal or external command,operable program or batch file.
gmake-378: *** [Debug/tmm.dxe] Error 1

This would appear to be due to the fact that I am running under Windows instead of UNIX because the tmm_export.mak file replaces

ADI_DSP=C:\Program Files\Analog Devices\VisualDSP 5.0

with

VDSP=C:Program\ Files/Analog\ Devices/VisualDSP\ 5.0

(replacing backslashes with slashes and spaces with backslash-space) which is what I assume is causing cmd.exe to choke.

Are there any environment variables or arguments to cmd.exe that I need to set to get gmake to run from cmd.exe? Can someone point me to the documentation which describes how to do this? How does the IDDE run the tmm.mak file properly?

I am using VisualDSP++ 5.0.6.0, IDDE 8.0.6.76 (Feb 12, 2009) under Windows XP Pro service pack 3.

Start to Use the BF561 Survillance kit by Avnet

analog@sgaur.hosted.jivesoftware.com — Sun, 15 Nov 2009 16:22:25 GMT

Hi.

Im beggining to use the survillance kit for BF561 from Avnet with a Micron Camera Sensor MT9D131 and I have the line_processing example but I cant see any image on the image viewer at the DSP++5.0. Does somebody is using these Avnet kit to image processing ? and can exchange some tips or knowledges on how can I use the kit to see the images, take pictures, film and recognize objetcs with these kit ?

Thank you.

Sytem services -port control - spi

analog@sgaur.hosted.jivesoftware.com — Wed, 21 Oct 2009 08:24:19 GMT

Hello,

In our design we are using the SPI interface through system services to create drivers for different peripherials. However, Blackfin is the SPI master allthe time and we do not use the SPISS line, which we do need for some GPIO. In system services port control the SPISS is enabled together with the other basic SPI signals every time a driver is opened, so I do not see other solutions than to modify the system services code in this case.(I really dislikes to do this.) Is there a possibility that this problem could be addressed in future releases of system services?

regards

Mads-l

Power-up Sequencing of ADSP-TS201S

analog@sgaur.hosted.jivesoftware.com — Sat, 31 Oct 2009 06:30:38 GMT

Hi All,

I am working on designing a custom baord consisting of Stratix-II FPGA and TigerSHARC ADSP_TS201S.
I am using an auxiliary FPGA Cyclone-II with DSP processor to interface with peripherals.

On referring the ADSP-Ts201S Sytem Design Guidelines Application Note, I found that the power-up
sequence for the DSP processor is such that it only needs to be ensured that the Vdd_dram voltage
(1.6V) is generated last. It says that there isn't any specific obligation to sequencing the generation
of Vdd/Vdd_a (1.2V) and Vdd_io(2.5V). So accordingly, I am following the sequence 1.2V followed by 2.5V
followed by 1.6V. This ensures that 1.6V is generated last.

But when I referred to ADSP-TS201S Silicon ANomaly List - Page 28

58. 03000373 - PLL Failure to Lock at Power-Up:

DESCRIPTION:
The PLL may fail to lock correctly to the SCLK input during power-up.

WORKAROUND:
Vdd/Vdd_a must be held low until after Vdd_io and SCLK_Vref are stable and within specification. Additionally, SCLK must be held high
or low until after Vdd/Vdd_a is stable and within specification. The following figure illustrates the workaround (followed by waveforms of sequencing)

According to the waveforms shown, it is required to generate Vdd_io(2.5V) first followed by Vdd/Vdd_a(1.2V).
But such a sequencing hasnt been mentioned in the design guidelines, although PLL power-up is one of the
critical requirements of a DSP-based system.

Can someone please throw light on this workaround? Is it possible to follow the sequencing as I have done presently.
Certain obligations might prevent me from generating 2.5V first unless I make drastic changes in my design.

Thanks and regards,
Sid

BlackFin 2D Graphics Lib

analog@sgaur.hosted.jivesoftware.com — Thu, 12 Nov 2009 08:50:12 GMT

HI ADI-Support,

I would like to use the BlackFin 2D Lib in combination with a BF561. In my application I am using an LCD connected via RGB 565 on the PPI interface.

I have two questions now:

1. The lib needs a pointer to ARGB to RGB888 conversion routine. Is it also possible to use adapt this function and provide an ARGB to RGB565 conversion instead.

2. The libadi_graphics2d.dlb is about 2.4 MByte. Is this the true size of the production lib or does there a smaller lib exists?

Thanks in advance for help!

Best regards

Thomas

problem with double precision number

analog@sgaur.hosted.jivesoftware.com — Tue, 27 Oct 2009 20:08:17 GMT

Hi everybody,

I've got a problem with operation with double precision number

for example in Matlab (with double precision arithmetic)

a = 1.570796326794897 radian (it is pi/2).

in hex a = 3ff921fb54442d18

cos(a)

6.123233995736766e-017

in hex cos(a) = 3c91a62633145c07

in Visual DSP++ v5 update 6

simulator ADSP-21369

a = 1.570796326794897 radian (it is pi/2).

in hex a = 3ff921fb54442d18

everything is the same

BUT cos(a) is

6.123233995736757e-017

in hex cos(a)= 3C91A626 33145C00

It clear that there is difference in last byte "07" is not "00".

Can you explain it or describe goniometric function in math.h in detail?

Thanks in Advance,

Regards,

Milos

*******

Settings in VisualDSP

Project option -> Processor -> double precision = 64-bit IEEE double precision

rfft2d_fr16 and ifft2d_fr16 problem

analog@sgaur.hosted.jivesoftware.com — Tue, 17 Nov 2009 20:09:22 GMT

Hi,

Im attempting to do an FFT/IFFT on an 8-bit image, but am having poor results with the following code, which simply attempts to do an FFT, then an inverse, to make sure that not too much precision has been lost. I guess I am uncertain whether or not I am scaling the data correctly? I am using VDSP 5.0, update 6.

The resultant image I get out of the IFFT vaguely resembles the input image, but with much precision lost....

Original Image:

----------------------

Output Image after IFFT:

-------------------------------------

// Calculate Twiddle

complex_fract16* t_t = (complex_fract16*)malloc(sizeof(complex_fract16)*64);
twidfft2d_fr16(t_t,64);

fract16* pDst= pInputMatrix;
unsigned char* pSrc = pI1;

// I am attempting to convert 8-bit image data

// to [1 -1], then convert to fract 16 data type?

for(int ii = 0; ii < 64*64 ; ii++)
{
 // Scale to 1 to -1
 float fVal = (*pSrc++);
 fVal = (fVal-128)/255;
 fract16 frac = float_to_fr16(fVal);
 *pDst++ = frac;
}

// Do the FFT

rfft2d_fr16(pInputMatrix,pTempMatrix, pOutputMatrix, t_t, 1, 64, 0, 0);
// Immediately do the inverse, to see what I end up with
ifft2d_fr16(pOutputMatrix, pTempMatrix, pFinalMatrix, t_t, 1, 64, 0, 0);

...

// Convert back to 8-bit?

for(int ii = 0; ii < 64*64 ; ii++)
{
 float fVal = fr16_to_float(pSrc->re);
 fVal = (fVal*255)+128;
 *pDst = (unsigned char)fVal;
 pSrc++; pDst++;
}

TDM Mode Sport Connection

analog@sgaur.hosted.jivesoftware.com — Fri, 20 Nov 2009 12:48:03 GMT

Hi,

I have few question regarding the SPORT TDM mode of operation.

1. How the sport signal pins needs to be connected for TDM operation?

2.Whether the external pin sport connectivity is same for different TDM modes(Transmit only, Receive only, Both transmit and receive)?

3. Suppose we connected one sport in TDM mode, Is it possible to opearte the Transmit and receive channels seperatly?

4. Is there any EE note availble?

5. whether the connectivity is same for both MAster and Slave mode of DSP?

Query regarding BF 537

analog@sgaur.hosted.jivesoftware.com — Tue, 29 Sep 2009 10:31:11 GMT

We are using Analog Device BF537 Blackfin processor (500MHz) in our product design. Currently we are in prototype testing stage.

When we got the new board we connected it to supply and checked all the supply on the Board.

The processor internal voltage was 1.2V.

We connected the JTAG cable and it was detected by the processor.

Four to five times we connected and disconnected the JTAG cable in a span of around 3 hours, suddenly the processor core voltage increased to 3.3V as the internal regulator output became 0V.

Vrout = 0V so fet was continuously ON and core voltage reached 3.3V

Now Vrout is not switching, can u please help.

Can you please suggest what may be the problem (Same thing has happened to two Prototype boards)

SHARC question

analog@sgaur.hosted.jivesoftware.com — Mon, 02 Nov 2009 05:01:20 GMT

Hi Sir ,

Main DSP used Flash leading , then leading the DSP by SPI bus . how can the multiprocessor share the Flash and EPRom ? could you send us some file about it ? thanks .

Best regards ,

Windy

Device Drivers not Activating from SPORT ISR

analog@sgaur.hosted.jivesoftware.com — Fri, 13 Nov 2009 07:54:13 GMT

Hi Guys,

We are working with the VDK on SHARC 21371 and defined device drivers for I/O interface . We are trying to activate the Device drivers from the SPORT0 interrupt but it is not activating.

If we call the function VDK_C_ISR_ActivateDevice(kIODevice) from the ISR it shoud hit the IOActivate case in the device driver Dispatch function. But it is not happening.

Can you guys help us ASAP it is holding the customer delivery.

Best regards,

Kishore.

Priority inheritance mutex

analog@sgaur.hosted.jivesoftware.com — Wed, 11 Nov 2009 08:13:20 GMT

I am trying to implemet a "Priority inheritance mutex" i.e. a mutex where the thread that has aquired the mutex runs at the same priority as the highest priority of all waiting threads. The purpose of these mutexes is to handle the "priority inversion" problem where a thread with high priority end up with waiting for a thread with low priority. Unfortunately was I not able to solve this on my own and would like to have some help:

- Has anyone done this and woukd like to post an example?

- Is there a way to ask VDK about the "owner" (last thread that aquired a semaphore/mutes)?

LDF CACHE characteristics changed unexpectedly in VDSP UPDATE 5.7

analog@sgaur.hosted.jivesoftware.com — Mon, 09 Nov 2009 03:11:58 GMT

I had some code running under 5.5. When I installed 5.7 and then activated my project -- was informed LDF had changed.

The ldf is always been changed as I switch from HPPCI-ICE session to Simulator frequently -- so took no notice.

However my code did not work.

In checking, I notice that the DCPLB_ADDR setting for memory 0x01000000 has been changed from DCPLB_ADDR6 to DCPLB_ADDR8

Any particular reason for this to happen?

HPPCI-ICE on Windows 7 - 64bit Edition

analog@sgaur.hosted.jivesoftware.com — Sat, 10 Oct 2009 16:31:13 GMT

I am running Windows 7 64bit edition on my PC. It supports Windows Vista 64 drivers for the most part. Is there a HPPCI-ICE driver that will work on a 64bit edition of any verion of Windows?

Thanks

Rick

Does BF51x RSI interface need pull-up resistances and ESD protected components?

tony.lxy@gmail.com — Fri, 20 Nov 2009 07:37:43 GMT

Q1:I want to using BF514 drive a SD Card by RSI interface. For a stable system, Does BF51x RSI interface need pull-up resistances?

Q2:As you know, SD card is a removable storage device. In real world electrostatic destory is common. Does RSI interface support a protect abiltiy for 8KV static ?

Thanks!

what type of FFT is suited for my application

analog@sgaur.hosted.jivesoftware.com — Fri, 20 Nov 2009 03:06:46 GMT

Hello guys.

i'm very new at using the blackfin processor, specifically the ADSP-BF537.

for my implementation, i will have take the fft of a signal coming from an electric guitar,

are there any sample fft programs that are similar to this type of application?

and what fft is best suited for this?

thanks in advance

Switching between LCD buffers in ADI_DEV_MODE_CHAINED_LOOPBACK

analog@sgaur.hosted.jivesoftware.com — Thu, 22 Oct 2009 10:04:14 GMT

Hi ADI Support,

I am using an LCD connected to PPI with two buffers in ADI_DEV_MODE_CHAINED_LOOPBACK.

Now I have two Frame Buffers for the LCD. I would like to write e.g. an image to first buffer while the second is looped in chained mode to the LCD output. When the first image buffer is processed and ready I would like to write this buffer to the LCD output and update the image on the second buffer. I have noticed that it is not possible e.g. with switch to the other frame in the callback in the chained loopback mode.

adi_dev_Write(LcdDriverHandle,ADI_DEV_2D,&LCDOutputBuffer[1]);

Do you have any suggestions?

Thanks

Regards

Thomas

BF533!Why can't my code return from the function of idle()?

analog@sgaur.hosted.jivesoftware.com — Tue, 10 Nov 2009 01:51:16 GMT

Hi,

I just use the BF533 and want to set the cclk and sclk in my main function. But I find that the processer can not return from the function of idle() sometimes. I think the PLL have not generate the wake up signal when it happens. Why?

*pSIC_IWR=1;

*pPLL_CTL = 0x2400;
ssync();
idle();
*pPLL_DIV = 4;

ssync();

Thanks!

Eval Board just died

analog@sgaur.hosted.jivesoftware.com — Tue, 10 Nov 2009 14:33:07 GMT

I was running a simple program (just a couple low-pass filters) using my ADAU1761 Eval board with USBi connection and then suddenly there was a click and no audio was passing through. All of the LEDs on the USBi board are now lit up...before this, only two LEDs lit up. I disconnected everything, the just connected the USBi board to my computer (disconnected it from the Eval board) and the LEDs are all still lighting up. Did my USBi board just die??

SDCards via SPI interface on Blackfins without SDController (BF537)

analog@sgaur.hosted.jivesoftware.com — Mon, 20 Jul 2009 11:47:50 GMT

Hello,

I got a Example code for SDCards via SPI interface on Blackfins without SDController (BF537), but it was written for another processor. So I made some adaptions for BF537, but the code does not work properly. It seems that the first 6 bytes are beeing transmitted correct, but the next not. Can anyone help?

DSP read back for data capture

analog@sgaur.hosted.jivesoftware.com — Wed, 04 Nov 2009 03:03:06 GMT

Hi there,

We're trying to read the value of a level detector from our uC and just having a bit of struggle understanding the datasheet.

Our meter is at address 2074 as expected, (data capture register), however all the tests we've done we couldn't get the correct value out of a read of this register. I think that the issue is related to the Program counter register setup and RS bits...

The datasheet states: "The capture count and register select values that correspond to the desired point to be monitored in the signal processing flow can be found in a file output from the program compiler"

My question is how can we get that desired point? Which compiler output file are you refering? Is that the trap.dat?

Would it be possible to use on an example as I'm sure that we can't be the only one wanting to read the value from the DSP.

Thanks a lot for your support,

Tony

Adau1701 evaluationboard?

analog@sgaur.hosted.jivesoftware.com — Thu, 19 Nov 2009 23:17:50 GMT

Hello,

For a Radio station, we want to make a DSP ADAU1701, to get a better sound.

But we do not know how to start, the budget we have is low, and now equal to $ 900 to spend on an evaluation board, is not the intention.

Is there any student or hobby version to get? or maybe a used board? or another way to do what to do with this super dsp chip?

We are very enthusiastic about this chip and sigma studio!

Please help ... Thnx.

ADSP21371 - ADAU1361

analog@sgaur.hosted.jivesoftware.com — Fri, 20 Nov 2009 09:27:49 GMT

Hi to all

I want to connect audio codec ADAU1361 to ADSP21371. For configuring the codec i use the SPIB. In some example i saw that is used flag signal. Is this signal is for setting the CLATCH signal tree times low. And how this is achieved?

ADAU1761 RMS detector problem

analog@sgaur.hosted.jivesoftware.com — Fri, 23 Oct 2009 07:51:50 GMT

Hello,

I have found what I believe is an issue with the RMS Table. It works as expected until it's input level drops below ~-75dBFS. Below this level the table appears to wrap and does not produce the expected values.

Is this a known bug/feature?

Ian.

Error by Flexible License Manager

analog@sgaur.hosted.jivesoftware.com — Tue, 17 Nov 2009 22:18:05 GMT

Hi,

I am facing a licensing issue with Visual DSP. I am working on Win XP and am using VDSP v4.5 on BF533 processor.

I installed Visual DSP on an application server (Win 2003 server) and I also validated a blackfin license on it. If I go and check the licenses I can see Validated (Permanent) in front of Blackfin. But when I try to open VDSP environment I get below error:

ERROR: Terminal Server remote client not allowed

Feature: VDSP-DEBUGGER

License Path: E:\AnalogDevices\VisualDSP4.5\System\license.dat

FLEXnet Licensing error:-103,577

It looks like it is a licensing issue. The license I have is a multiple use license and the only other system I have used it is on my personal machine. Is there an issue to use this on an application server. Is there something specific I need to do to make this work.

Thanks

Megha

Spi connection with ADF7021

analog@sgaur.hosted.jivesoftware.com — Tue, 10 Nov 2009 10:01:30 GMT

Hello,

I'm working on an ADF7021 with a MSP430F5438 processor and the Spi connection get me some troubles.

I try to set correctly the configuration connection : MSP430 as Master and ADF70 as Slave.
I can make readback communications (the answer of the ADF is correct) but I'm not able to program a register.
You could find a screenshot of the MSP's signals with this message.
Does someone know what I forgot to do during this kind of operation ?

Cheers.

PS : This forum isn't compatible with the great Opera Web Browser

Updates

analog@sgaur.hosted.jivesoftware.com — Wed, 11 Nov 2009 12:33:01 GMT

Hi , to all

I want to know wether is there some new updates for VisualDSP++ 5.0. ? i was told about updates 7!!

UART BF537 Recieve Data error

analog@sgaur.hosted.jivesoftware.com — Wed, 16 Sep 2009 05:05:38 GMT

Hello ,

Is there a sequence for Setting the UART and PORT .

I am asking this because wen we Inialize the UART and then Inialize the port we see that 1st Byte recieved is 0xFF this doent happen all the time but some times and once seen then keeps on appearing .

But If the Port is inialized first and then the UART we see there is no problem .

Is this a problem with Seqence .

Please let me know .

Thanking you

system services dma callback

analog@sgaur.hosted.jivesoftware.com — Wed, 23 Sep 2009 07:02:37 GMT

hello,

I am using the system services and driver model to write a driver for the AD5663 DAC. I am building it upon the ADI sport driver with DMA using a two dimensional "ping pong" buffer. The idea is to fill one subbuffer, while the DMA transfere the other. This works fine, but I see a potensial problem in the way I get DMA events in my interrupt callback. The only event i get is the ADI_DEV_EVENT_SUB_BUFFER_PROCESSED. I never see the ADI_DEV_EVENT_BUFFER_PROCESSED. I had hoped to be able to determine which subbuffer the DMA had completed this way. My next approch was to use the pointer to the buffer received in the callback, but this pointer allways points to the start of the whole buffer, so there is no indication of what buffer that is actually processed. By examining system services source (adi_dma.c) I see the the following statements which I belive confirms my observation:

// CASE (circular)
case ADI_DMA_MODE_CIRCULAR:

            // determine if it's an inner loop interrupt or an outer loop interrupt
            if (pChannel->Config->b_DI_SEL == ADI_DMA_DI_SEL_OUTER_LOOP) {
                Event = ADI_DMA_EVENT_OUTER_LOOP_PROCESSED;
            } else {
                Event = ADI_DMA_EVENT_INNER_LOOP_PROCESSED;
            }

            // override the pArg callback parameter to be the buffer start address
            pArg = pChannel->StartAddr;
            break;

Should i use another DMA model in my case? Is there a way to be absolutely sure that my program is syncronized to the DMA buffer handling? When I stop the transfere, will the DMA be re-initialised to start with a clean buffer structure or may it start in the subbuffer?

mads-l

Reading DMA registers giving error values

analog@sgaur.hosted.jivesoftware.com — Mon, 13 Jul 2009 13:27:02 GMT

Hi all,

We are using BF-533 EZ-Kit Lite on VDSP5.0 with update4. I have written small code to read the values in DMA registers. Here i am giving the code i ahve written. Except start address and current address, other values are read from some other locations. If anybody having what are precautions to take care or my code is having bugs, please inform.

#define DMA_CHANNEL_OFFSET 0x40

.section program;

.global _main;

_main:

     R0 = 1;

     R1.l = 0x0C00;
     R1.h = 0xFFC0;//DMA_BASE_ADDR;

     R2 = DMA_CHANNEL_OFFSET;

     R2 *= R0;
     R1 = R1+R2;

     P0 = R1;
    R3 = [ P0 + 4];       // Start Address
     SSYNC;

R4 = [ P0 + 36];       //current Address
SSYNC;

R5 = [P0 + 16];        //x count
SSYNC;

R6 = [ P0+ 20];       //xmodify
     SSYNC;

R7 = [ P0 + 24];        // ycount
SSYNC;

    IDLE;

_main.end:

with regards,

sunil

How Can I do multipoint FFT on data (32K) sitting on External SDRAM?

analog@sgaur.hosted.jivesoftware.com — Mon, 20 Jul 2009 08:33:29 GMT

I have ADSP 21368 based custom board How Can I do multipoint FFT on data (32K) sitting on External SDRAM? Is it possible to do it without copying it in internal memory?

Thanks in advance.

clickless SW Slew - Growable Single Vol Ctrl issue

analog@sgaur.hosted.jivesoftware.com — Mon, 14 Sep 2009 08:49:34 GMT

Hi,

Again I've found a very strange issue with the clickless SW Slew - Growable Single Vl Ctrl block. The schematic is attached, I'm using ADAU1445. The level is set to zero at the compiling time, so once the program and parameter are loaded, I suppose I could see the input signal coming out of the output ports, but I couldn't see any thing coming out. With the same schematic except the vol ctr being replaced with No Slew (standard) version, everyting just works fine. Is there anything special I need to do to use the clickless SW Slew volume control? Thanks.

DMA TS101

analog@sgaur.hosted.jivesoftware.com — Wed, 11 Nov 2009 08:06:15 GMT

Hi ,

I have a question with regards to Internal memory <--> External memory DMA operation on TS101.

When the Destination TCBs DP - TY bit is set to 100 and

DI address is set to 0x00000000

1.Will the DMA work , if so will it work as Internal memory <--> internal memory DMA or

2.Will it consider as illegal configuration to DMA channels TCB registers (DP register) and generate a Hardware Interrupt .

Please let me know with regards to this.

Thanking you

With best regards and wishes

CMOS Sensor Device Driver

analog@sgaur.hosted.jivesoftware.com — Sat, 10 Oct 2009 04:09:05 GMT

Hi guys!

I found something in the Visual DSP++ 4.5 directory that appears to be a device driver header file for the Micron MT9V022 CMOS Sensor. This is exactly located in the VisualDSP++ 4.5/Blackfin/include/drivers/sensor/micron folder with the header file name being adi_mt9v022.h. I understand that this file contains the different function prototypes that would be used by the Blackfin board in order to run the sensor. I believe the function prototypes include register values that are only obtained from the data sheet of the sensor. Thus, as the sensor varies, so too will the register values.

Now, due to these realizations, I've come up with several questions that I badly need to be answered. First question is: Do I simply need to obtain the datasheet from the manufacturer and change the values found in the driver with the values found on the datasheet? Second question is: What are the other things that I need to modify in order for the modified driver to work? Third question is: Is there an available device driver for the MT9V125 CMOS Sensor?

Please guys, if there is anyone out there who had experience working on interfacing the Micron MT9V125 CMOS Sensor to the Blackfin boards, could you please help me? I really would appreciate your help.

Sincerely,

Allan

EXTERNAL PORT DMA OPERATION

analog@sgaur.hosted.jivesoftware.com — Fri, 30 Oct 2009 06:38:45 GMT

We are using ADSP 368 SHARC processor and VisualDSP++ 5.0. We are transferring data from external memory to internal memory through DMA Channel 1, The DMA register initialization are as below -

*(volatile int *)IIEP0 =   data;              // data is declare as a int array in the code

*(volatile int *)IMEP0 = 1;

*(volatile int *)ICEP0 = 64;

*(volatile int *)EIEP0 = (volatile unsigned int *)0x04F82000;                  // address for external momory (fifo)

*(volatile int *)EMEP0 = 0;                        // since our external memory is a fifo, so external modifier is zero.

*(volatile int *)EBEP0 = (volatile unsigned int *)0x04F82000;

My DMA Operation is happening, After examining the internal memory data, I found that each word is repeated twice e.g. 0^th and 1^st element contains same data, 2^nd and 3^rd element contains same data value. If I do this data transfer without DMA mode the data word is coming correctly. External BUS with is set for 16bit.

Please suggest.

Thanks in Advance.

What can I do that to use the standalone debug agent in my target boards

analog@sgaur.hosted.jivesoftware.com — Wed, 28 Oct 2009 09:50:14 GMT

Our firm buy the standalone debug agent, 21375 EZ-KIT Lite, VDSP++, ADZS-HPUSB-ICE, 21469 EZ-Board.

We develop our target boards with ADSP-21375, but we lack ADZS-HPUSB-ICE for develop our software.

What can we do that to use the standalone debug agent in our target boards

Expressions Window: ERROR: Unknown variable or symbol

analog@sgaur.hosted.jivesoftware.com — Thu, 29 Oct 2009 06:12:46 GMT

Hi,

I am trying to debug a BF537 based application, and experiencing an abnormal behavior from the VDSP 5.0. The "Locals window" for that particular program does not display anything when I am "single-stepping" through the program. Similarly the "expressions window" is giving "ERROR: Unknown variable or symbol" for all the expressions and "local" variables which otherwise would have evaluated to correct values when "single-stepping" through the program. However only the "global" variables are displayed properly in this window.

This has made almost impossible for me to debug that particular program. (Other programs run fine). What could be the problem. Please anybody help me out. It's urgent.

Best Regards,

Asif Habib

External SDRAM doesn't work on 96kHz...

analog@sgaur.hosted.jivesoftware.com — Tue, 10 Nov 2009 14:19:34 GMT

hi....

when I link my project (reverberation via SIMULINK embedded IDE link) it works fine on 48kHz, but when I try it on 96kHz it only talks thru...

thats why the data section for reverberation is on SDRAM....because for internal on-chip memory it is too large..

an other problem is that I try hard to flash the project....I use the default PROM > hex > 8bit > .ldr and flash it with the flash programmer successful...but it don't consider the SDRAM

see attachment for linker file..............

Wavelet Transform C / C++ for visual dsp 4.5++ in DSP SHARC

analog@sgaur.hosted.jivesoftware.com — Fri, 13 Nov 2009 13:11:16 GMT

Does anyone know how to program in C / C + + to create a wavelet transformation on the SHARC DSP with visual dsp + + version 4.5? Or example programs for wavelet transform functions in C / C + +? Please. Thanks

ADV7184 Video Decoder Schematic

analog@sgaur.hosted.jivesoftware.com — Thu, 08 Oct 2009 16:13:42 GMT

Hello,

I have a question about the 'typical circuit connection' on page 111 of the ADV7184 data sheet.

On the schematic it shows the ELPF pin (near bottom right of chip) connected to 'PVDD' via two capacitors & a resistor. I'm a bit confused as to where this PVDD is. Is it the 1.8V supply near marked 'PVDD' near to the top of the chip? I've attached a jpeg diagram illustrating my references.

Many thanks,

Owen

RMS results

analog@sgaur.hosted.jivesoftware.com — Thu, 19 Nov 2009 19:18:00 GMT

Hello,

I have recently received the ADAU1761 evaluation board. One thing I have noticed is that the RMS results using the RMS squared envelope and then the square root function work fine for frequencies above 50Hz. When I try an input frequency of 2Hz using the tone input, the results go up and we end up with a 30% error. I have found that if I can the TC of the envelope down to 5, reults are beeter with a 2% error. The problem with that scenario is the response time of the function. Changing the sampling rate did not affect the results either. Any suggestions will be appreciated.

Thanks.

Help needed for Development Board selection...

analog@sgaur.hosted.jivesoftware.com — Mon, 12 Oct 2009 06:34:31 GMT

Hi,

Iam searching for a devolopment board for my project. It requires the following features :

Dual DSP core
3U cPCI backplane support
Ethernet interface
Serial interface
JTAG interface for debugging & sytem development
Both Windows/Linux Driver support.

I came across this board -> SI-C33DSP-cPCI, but this board doesnt have ethernet interface & has only a single core. Please Suggest some boards with the given specifications.

Thanks in advance,

Rizwan

Incomprehensible linker error: failing to place constant at absolute address.

analog@sgaur.hosted.jivesoftware.com — Thu, 05 Nov 2009 13:12:21 GMT

I want to place a constant at absolute address, but linker issue:

[Error li1173] Failed to extract symbol '_Firmware_Crc' needed for absolute placement.
Symbol is embedded in object (.epcrodata, .epcrodata.end).
.

My source file ver.c looks as:

const unsigned short Firmware_Crc = 0xffff;

My .ldf file contains:

PROCESSOR p0
{
...

RESOLVE(_Firmware_Crc, CRC_ADDR)

KEEP(_start, _main, ___inits, _Firmware_Crc)

SECTIONS
{
...

      ASYNC0_constdata
      {
        INPUT_SECTION_ALIGN(4)
        INPUT_SECTIONS($OBJECTS{requiredForROMBoot}(constdata) $LIBRARIES{requiredForROMBoot}(constdata))
        INPUT_SECTIONS($OBJECTS(constdata) $LIBRARIES(constdata))

INPUT_SECTION_ALIGN(2)
INPUT_SECTIONS_PIN_EXCLUSIVE(ver.doj(constdata))

} > MEM_ASYNC0
...

CRC_ADDR is equal to 0x2000FFFE (last two bytes of 64Kb, because my firmware has size less then 64Kb)

What do I wrong? And what a misterious object .epcrodata?

P.S. I examined assembler file ver.s produced by compilator. This is a piece of it:

.section/DOUBLE32 constdata;

      .align 4;
     .epcrodata:
      .type .epcrodata,STT_OBJECT;
     _Firmware_Crc:
      .global _Firmware_Crc;
      .type _Firmware_Crc,STT_OBJECT;
      .byte =
       0xFF,0xFF;
     .epcrodata.end:

So my constant is placed inside of .epcrodata. But what I should do to fix this problem?

No VROUT output from BF537 after power ON

analog@sgaur.hosted.jivesoftware.com — Fri, 23 Oct 2009 04:58:55 GMT

We are using ADSP BF537 as one of our custom Board.

The processor which we are using is silicon revision 0.3

When we powered up the Board for First time the VROUT output is not coming and it is always 0V. What may be the problem

How regulator output can come up.

Simple Mute with GPIO?

analog@sgaur.hosted.jivesoftware.com — Thu, 19 Nov 2009 21:11:15 GMT

How would I implement a simple mute function in SigmaStudio, using a push-button on a GPIO? I don't want volume control, just a single button that cleanly mutes/unmutes the audio.

Thanks!

--> freddie

MDIO interface on BF518

analog@sgaur.hosted.jivesoftware.com — Fri, 11 Sep 2009 01:52:54 GMT

Hi,

Does the MDIO interface on BF518 can be configured as slave device? Thanks!

Device serial number

analog@sgaur.hosted.jivesoftware.com — Fri, 20 Nov 2009 17:58:29 GMT

Is it possible to access the device serial number or any identifier unique to the device?

Thanks

Using cascaded SDRAMs with ADSP-TS201S

analog@sgaur.hosted.jivesoftware.com — Fri, 30 Oct 2009 06:47:01 GMT

Hi All,

I am a newbie as far as usage of TigerSHARC processor is concerned.

I am preparing a custom board using ADSP-TS201S and Stratix-II FPGA.

To interface peripherals, I am using an auxiliary FPGA Cyclone-II between ADSP-TS201S and peripherals. Due to certain constraints, I am using 2X16-bit SDRAMs cascaded into 1X32-bit SDRAM. I have cascaded data lines D0-D31 acordingly and using shared address bus and control signals for both.

My question is - Since I am accessing only 32-bit data (word) each time, shal I use only LDQM signal to connect DQML and DQMH signals of both SDRAMs? Will HDQM remain unused in this case, since it is used only for 64-bit data accesses?

Also, the evaluation kit shows using different SDRAM clocks for the two cascaded SDRAMs used. Can I use a single clock source and make connections in a star-shaped format for the same?

Thanks and Regards,

Sid

EZKIT-21369

analog@sgaur.hosted.jivesoftware.com — Fri, 13 Nov 2009 13:51:11 GMT

The default sampling rate for DAC is 48kHz. How to modified to 16kHz or 8kHZ?

VisualDSP++ editor can work with max 2049 characters in one row

afinko@gmail.com — Fri, 16 Oct 2009 15:39:20 GMT

If I want to add more than 2049 characters in one row, the VisualDSP++ editor automatically disassembly the row in more rows with 2049 characters.

However, in this case, the compiler take the next row as a new line, and mostly produce an error.

Is there a way how to set the editor to work with larger row than 2049?

Is there some special character, that I can add at the end of the row so the compiler will take new row as the same line?

Thanks,

Afi

LDF Files on BF561 with VDK

analog@sgaur.hosted.jivesoftware.com — Tue, 10 Nov 2009 08:24:34 GMT

Hi ADI support,

I am using VisualDSP5.0 Update6 and a dual core application so one for each core. The first core is managing also the Lwip Stack. So for this I am using the Project wizard that gives me all the settings for a LwIP Project. My question is now in comparision to other project e.g. Booting (C) with Video in out it gives a other structure with five subprojects and one LDF file. With the Wizard LWIP Project I have two Linker description files in the project created by the wizard. So what is the best way to use for a project.

What do you suggest at the End I will need also to initalize some shared L2 and L3 memory in my project and a semaphore which is posted to coreB. Can I easily at SM2 and SM3 subprojects to my LWIP project?

Please advise!

Best regards

Thomas

JTAG not connecting

analog@sgaur.hosted.jivesoftware.com — Wed, 21 Oct 2009 15:56:20 GMT

Hi,

I am using ADSP-BF537 in one of our custom board.
Since yesterday this board was working fine. But today when we are trying to connect the JTAG, its not getting connected and i am getting the below error

We tried probing all the JTAG signals. The TDI pin is always low. (when we are connecting thru JTAG)
By default i am getting the system clock but when i am trying to connect the JTAG thru VDK , the system clock is not coming.

Can u please help us.

attachment is the screen print of erre

Fast Table lookup

analog@sgaur.hosted.jivesoftware.com — Tue, 23 Jun 2009 14:46:32 GMT

I need to perform a lookup translation of 5M 10-bit values (in 16-bit words) utterly as quickly as possible. That, of course, calls for an assembly language implementation of this C code. This is my first project using Blackfin Assembler so some assistance will be appreciated. Is this the fastest way for me to do this? Later, I'll ask about how to alternate chunks through L2 cache while this munches on the other chunk. Thanks!

extern unsigned short LookupTable[1024];

void Translate( unsigned short *pIObits, int iLength )

{

int i;

for( i = 0; i < Length; i++ )

{

IObits[i] = LookupTable[ IObits[i] ] ;

}

Below is my Assembly code version but the Assembler complains

"Preg read after write which requires 4 extra cycles" at the assignment into R0.H.

.extern _LookupTable;

_Translate_asm:
P2 = R1; // Length

I0 = R0; // pIObits

P3.L = _LookupTable

P3.H = _LookupTable;

R2.H = 0; // Clear high word

M0 = 2;

// Translating two words per iteration
LSETUP( LoopTop, LoopBottom) LC0 = P2 >> 1;
LoopTop:

R0 = [I0]; // Load two 10-bit values in separate words
R0 <<= 1; // Use each as an index into a word table

R1 = PACK( R2.H, R0.L); // Sample N+1

R0 = PACK( R2.H, R0.H); // Sample N

    P1 = R1;
    P0 = R0;

    R0.H = W[P0 ++ P3]; // Preg read after write which requires 4 extra cycles
    R0.L = W[P1 ++ P3];

    [I0++M0] = R0; // Store translated words
LoopBottom:

RTS;

_Translate_asm.end:

Is this the best, fastest way to do this? What can I do to get rid of the warning?

Advice and suggestions will be appreciated!

Bruising my nose on the learning curve...

dmp

Performance of FIR accelerator

analog@sgaur.hosted.jivesoftware.com — Tue, 10 Nov 2009 11:25:53 GMT

Hi,

I would like to use the SHARC 21469 for professional audio processing. In the last days I dealt with the accelerators.

I want to process the audio samples sample based to minimize the delay. For example I want to use the accelerator for computing a FIR filter with N taps. In the hardware reference I found following formula which describes the performance of the FIR accelerator:

(TCB load + 4 × N + W(N/4 + 2)) × C where:
• N – Number of taps
• W – Window size (--> W = 1 in case of sample based)
• C – Number of channels
• TCB load = 30 peripheral clock cycles
• 4 × N – Number of cycles for loading coefficients and data considering
two cycles for write
• N/4 + 2 – FIR compute cycles considering four pipelined MACs

So in case of sample based processing the overhead for loading coefficients and data (delayline) would be 16 times bigger in comparison to the computation of the FIR filter because for each channel coefficients and data (delayline) have to be reloaded from the internal memory via DMA.

If this is right I would be impossible to use the accelerator for realtime processing in case of 96kHz samplerate.

I would like to know if my conclusion is correct or if there any posibillities to reduce the overhead.

Best regards,

Marc

ADIS16350 - sample rate modes

analog@sgaur.hosted.jivesoftware.com — Sat, 24 Oct 2009 16:34:46 GMT

Hello,

I have a problem with switching the device to a normal mode, fast mode works well. The frequency of oscillator is 1,843,200 Hz and frequency of SPI serial clock is set as fosc / 16 so it is 115,200 Hz. According datasheet this frequency is possible in both modes. Could you please tell me what I am doing wrong?

Thanks.

Ladislav

BAD LINK ON VISUALDSP++ RUN-TIME LIBRARY FOR SHARC

analog@sgaur.hosted.jivesoftware.com — Fri, 20 Nov 2009 20:07:57 GMT

On the 21469 Manuals page, the link for the last version of the run-time library points to the C compiler manual.

Please, review it.

German

need help for choosing DSP-development boards

analog@sgaur.hosted.jivesoftware.com — Fri, 13 Nov 2009 14:06:13 GMT

Hi to all!

i'm new here and i really need help for my project... so i have a DSP-project from my professor for analyzing an analog signal..

the analog signal is about 5-10 MHz
the AD Converter should have 10-20 MHz sample rate
the DSP-card has sufficient clock rate
the data transfer between them an PC also need to be fast enough

well i have include the block diagram for the application... my friend had suggest to use MCU MSP430 from TI for the ADConverter and DSP-card TMS320, but it doesn't do right to this project...and i'm really confused in how to choose the development boards between black fin, sharc and sigma dsp.. or perhaps there's another suitable way?

thanks before

Ali

Theory: Continuos FT and DFT

analog@sgaur.hosted.jivesoftware.com — Mon, 02 Nov 2009 03:18:16 GMT

Hi. I can't find a place to discuss on theory. So, i decide to post it here. Hope that anyone can answer for query..

FYI, i read the Understand Digital Signal Processing.pdf

Background:

From the book, When sampling a continuos time-domain function, having a CFT, and take the DFT of those samples, the DFT results in a frequency domain sampled approximation of CFT.

Question
Why can we use the output of CFT to perform the DFT?

Reason to ask:The output of continuous fourier transform(CFT) is in frequency domain ( continuos signal ) while the input of DFT (before tranformation) have to be in discrete.

Thanks a lot

Location of in TS201 directory

analog@sgaur.hosted.jivesoftware.com — Wed, 16 Sep 2009 00:31:46 GMT

I am rebuilding a TigerSHARC project from a couple of year back using an earlier VDSP

The system is complaing about could not open source file "heap.h"
#include <heap.h>

I searched C:\Program Files\Analog Devices\VisualDSP 5.0\TS\include, but could not find it

Anybody know where that is now hiding?

Thanks

Ethernet pingout

analog@sgaur.hosted.jivesoftware.com — Mon, 26 Oct 2009 12:00:10 GMT

I am using ADSP BF537 in one of our custom Design

I have a ethernet Issue
Can you please let us know
How to Ping out to the external server from target Board using LWIP thru VDK

Connecting AV-EXTENDER for BF 537 to a LCD TV via RGB component.

analog@sgaur.hosted.jivesoftware.com — Fri, 18 Sep 2009 15:04:16 GMT

Good Am/Pm;

I noticed that the AV-EXTENDER has a RGB component OUTPUT ports.. and i also saw it on the schematic diagram. so i assume that the AV-EXTENDER would allow me to connect it to a LCD TV through the RGB component.

It is possible to display the output of the AV-EXTENDER to the LCD TV via RGB component? Are there any example codes available? the sample code in the examples folder of visualdsp++ only deals with LCD displays via the PPI port. Please help me.

Thank you,

Robbie Ko

ADSP embeded module

analog@sgaur.hosted.jivesoftware.com — Thu, 29 Oct 2009 10:55:46 GMT

Hi Sir ,

about the link between VisualDSP++ and MATLAB , we can't find the ADSP embeded module from MATLAB , but we can find the TI's embeded module , can you help us to solve this problem ?

Thanks .

Best regards ,

Windy

"talkthru analog in-out" example program do not work

afinko@gmail.com — Thu, 22 Oct 2009 18:46:03 GMT

I tried the "talkthru analog in-out (asm)" that is located in:

...\Analog Devices\VisualDSP 5.0\213xx\Examples\ADSP-21375 EZ-KIT Lite\

with my ADSP 21375 EZ-KIT Lite, but it do not work

Interrupt works well, it is generated according to the 48 kHz, but from ADC I receive all the time the value 0x00EAABF500.

I tried also to sent to the DAC's data from manually generated buffer instead of output from ADC, but at the output from the DAC is nothing.

I tried also the example program "block based talkthru (c)" located at the same directory. All the buffers Block_A, Block_B, and Block_C are filled with the value 0x00EAABF500. Input sound is not going through output.

Another programs that do not use codec work well at this board, also SDRAM is working correctly, but I am not able to manage the codec.

Can anybody try these examples on the ADSP 21375 EZ-KIT Lite, so I will know if the problem is in code, or in my hardware.

The "talkthru analog in-out (asm).zip" and "block based talkthru (c).zip" is attached.

Thanks,

Afi

optimized goertzel algo for Blackfins

analog@sgaur.hosted.jivesoftware.com — Fri, 14 Aug 2009 06:17:28 GMT

hi !

is there any optimized code for a goertzel algorithm which is usable for blackfins?

regards chris

Do AD plan to make sharc's 214xx with 5Mbits RAM in TQFP's package?

analog@sgaur.hosted.jivesoftware.com — Fri, 23 Oct 2009 07:14:58 GMT

According sharc's 214xx manual 214xx is a very good processors with the big internal memory and the supports of VASI and DDR-II.

Do AD plan to make sharc's 214xx with 5Mbits RAM in TQFP's package?

Schematic of the Evaluation Board: EVAL-AD1974AZ

afinko@gmail.com — Wed, 28 Oct 2009 10:15:28 GMT

Where can I find the schematic of the evaluation board: EVAL-AD1974AZ?

Even a block schematic of what is on the board, or photos would be helpfull.

561 power , one core in IDLE

analog@sgaur.hosted.jivesoftware.com — Tue, 27 Oct 2009 14:16:10 GMT

when I use the 561 and one core does nothing :

"IDD-IDLE : VDDINT supply current for idle activity. Idle activity is each core executing the IDLE instruction"

how much Iddint-dyn is saved ?

I did not see this point in EE293

regards

Eran

Interfacing TS201 with dpram

analog@sgaur.hosted.jivesoftware.com — Mon, 16 Nov 2009 14:29:05 GMT

In our board we have blackfin and Tigersharc processor.

We need to connect a dpram between blackfin and Tigersharc.

(The board has FPGA which controls the R/w,OE signals of dpram)

We have to perform 32 bit access to dpram from both blackfin and tigersharc

32 bit 32bit

BF561 ------------>DPRAM <----------------TS201

On blackfin side address is connected to dpram from bf_addr02..

On Tigersharc side address is connected to dpram from Ts_addr00..

Is that above address line connection a right method for performing 32 bit access to dpram from TS201 ?

I have attached the schematic page of the dpram.

Please review it and reply me

If anybody already have some reference schematic of interfacing dpram with tigersharc TS201

Please attach me

Mahendra

PLL ADF4106

analog@sgaur.hosted.jivesoftware.com — Mon, 16 Nov 2009 19:34:12 GMT

Hi,

I'm seeking help in programming analog devices PLLs (ADF4106). The eval. board comes with a software but I need to write a C or matlab code to program the device.

I look forward to any help or advice,

Thank you.

EPPI Sychronization problem on BF548 EZ-kit

analog@sgaur.hosted.jivesoftware.com — Fri, 18 Sep 2009 01:24:17 GMT

Hi all,

I am doing a video project,using BF548EZ-Kit and OV7620 image sensor. The sensor is connected directly to the borad via EPPI1 interface. For testing, a single frame can be captured after setting up the DMA13 and EPPI1 configuration. I use image viewer to display a image with a start address that I specified in the DMA start address. The problem is every time I got a frame, it seems that the image is not sychronized well.It can be seen from the figure I attached below.

The EPPI status register reports a error (EPPIx_STATUS = 0x0024). i.e. Frame Track Underflow Error. When the image I got is correct(the whole frame), the error disappears. I struggled to figure out where the problem is but without success. My configuration of EPPI1,DMA and port muxing setting is as follow. Any help would be appreciate!

void InitPorts(void)
{

//activate PortE 14,15 for TWI SDA and SCL
*pPORTE_FER = Px14 | Px15;
ssync();

// set FERF for PPI Data 0-7
*pPORTD_FER = 0x00FF; //PortD is PPI1
//ssync();

// set FERF for PPI CLK PORTE is for PCLK(PE11),PFS1(PE12),PFS2

(PE13).
*pPORTE_FER = 0x3800; //0011 1000 0000 0000
ssync();
}

void InitDMA(void)
{
*pDMA13_START_ADDR = Frame; //(0x300000)

*pDMA13_X_COUNT = PIXEL_PER_LINE; //320

*pDMA13_X_MODIFY = 0x1;

*pDMA13_Y_COUNT = LINES_PER_FRAME; //240

*pDMA13_Y_MODIFY = 0x1;

*pDMA13_CONFIG = DI_EN | WNR | WDSIZE_8 | DMA2D | AUTOBUFFERMODE;
ssync();

}//end Init_DMA

void InitEPPI1()
{
    // - EPPI disabled first
    // - EPPI in receive mode
    // - GP 2 mode

//Skipping enabled

//FS1 is active high and FS2 is active low, FS1 and FS2 sre

connected to Hsync and Vsync respectively.

// - sample data on rising edge and sample/drive syncs on rising

edge
// - DLEN = 8 bits
*pEPPI1_CONTROL = 0x0006592C;
ssync();

// total lines is 640
    *pEPPI1_LINE = 640;
    ssync();


    //The PPI is set to receive 525 lines for each frame
*pEPPI1_FRAME = 240; // OV7620 default mode is interlace with 240

lines per frame

ssync();
}

Problems about booting from nand flash on BF548

analog@sgaur.hosted.jivesoftware.com — Mon, 19 Oct 2009 07:55:28 GMT

I've designed my own Bf548 board. Howerve I want to boot from nand flash. Is there any SOP for this kind of work? I've ask my FAE. It seems ADI has no such sample code. I know there are some samples about booting uclinux from nand. I just want to start the processor and make LEDs blink first. Beside, is anyone use the sample in "C:\Program Files\Analog Devices\VisualDSP 5.0\Blackfin\Examples\ADSP-BF548 EZ-KIT Lite\Services\File System\NAND"? It worked on my Ez-Kit but failed on board. The error message says I need a FTL license. Does it mean it only work with ST nand flash on Ez-Kit and don't support my Samsung Nand flash? Any opinion is welcomed~ Thanks~

Blackfin C code and predicted jumps

analog@sgaur.hosted.jivesoftware.com — Wed, 04 Nov 2009 13:16:38 GMT

Have been looking at Chapter 4 in the Blackfin manual and I understand issues around predicted and non-predicted jumps at the hardware level.

This is a question at the software level related to hardware level

If the C-compiler generates the instruction IF CC JUMP XXXX

Then does that default to IF CC JUMP XXXX(np) or IF CC JUMP XXXX (bp) as I can't find that information in the hardware manual.

I am going to presume that the code defaults to the non-predicted IF CC JUMP XXXX(np)

Regardless of whether I am right or wrong -- if there a C pragma (or a compiler option for this one file) that can be used to force the compiler to do a predicted or non predicted if?

ADAU1761 Analog performance

analog@sgaur.hosted.jivesoftware.com — Thu, 22 Oct 2009 12:22:14 GMT

Hello,

I am implementing a new design using the ADAU1761 and currently have a couple of performance issues that I need to resolve. Both of the issues below are present on the development board ADAU1X61EBZ and my own hardware.

1. The audio from the ADC (line input) has a low level (~-80dBFS) spurious 'birdy' that varies in frequency with time but usually settles around 5.5KHz. It's frequency can be changed / modulated by touching a scope probe on the line input pin of the 1761. I have been unable to supress this spurious response.

The spurious 'birdy' is only present when the line input is connected to the ADC in the mixer config.

2. What is the isolation between the analog inputs and the analog outputs? I can't see this specified on the datasheet anywhere. To test this I am driving the line input with 1VRMS sinewave at 1KHz, and measuring the output with the input mixer paths disabled. A far as I can tell the isolation is less than 50dB which seems rather poor.

Any help greatly appreciated.

Ian.

Writing into Imask register.

analog@sgaur.hosted.jivesoftware.com — Wed, 11 Nov 2009 10:11:03 GMT

I couldn't write into IMASK register though I can write into SIC_IMASK register as below

*pSIC_IMASK = 0x00010000;

*pIMASK = 0x081f; //Throws excause 2e [ Not allowed in user mode]

any input is appreciated.

Born.

CLK_CFG1-0

analog@sgaur.hosted.jivesoftware.com — Sun, 01 Nov 2009 10:33:30 GMT

Hi to all

I don`t understand what exactly are pins CLK_CFG1-0 for? In the HR manual it says that they determine tha Core to CLKIN ratio, but int datasheet its says that these pins determine the Core to ClKOUT ratio. So how i should connect them , i want to use PLL to configure the Core clock after reset, so is there importance what is the value of these pins?

Calling rfftN from ASM

afinko@gmail.com — Thu, 15 Oct 2009 15:12:27 GMT

I want to compute 1024 point real radix-2 FFT on ADSP-21375 EZ-kit Lite.

I found in VisualDSP++ 5.0 Run-Time Library Manual for SHARC Processors the example how to use this library, but it is for C code. However, the routines are written in ASM (rfft_simd.asm).

I will not use any C code in my project.

Is there any example on how to use "rfft_simd.asm" from ASM main file?

The problem is, that I do not know which pointers are used for input and output.

E.g. rfft_1024 is calling _cfft512_simd and _cfft512_simd is calling ___bitrev_simd.

In "bitrev_simd.asm" is clearly written which register it is using:

*           Calling Parameters
*                R0 --> Input buffer
*                R1 --> Output buffer
*                R2 --> Length of buffer
*
*           Return Registers
*                R0 --> Modify value
*                R7 --> Log2(N)
*
*           Altered Registers
*                R2, R4, R7, R8, R12,
*                I4, M4
*                I3, M3
*                I2, M2
*                I5 (used by function, preserved on entry)

But in rfft_1024 and _cfft512_simd it is not written and I am a bit confused.

I will need to compute 1024 point real radix-2 FFT lot of the times for many inputs from another sources in a complex main program.

Therefore, I am planing to edit "rfft_simd.asm", to add _cfft512_simd and ___bitrev_simd inside one function and remove non necessary things such as:

#if ( RFFT == 16 )
#define LENGTH    16
#define NAME      rfft16_simd
#define TWIDDLE   ___tc16
#define CFFT_HALF   _cfft8_simd
#elif ( RFFT == 32 )
#define LENGTH    32
#define NAME      rfft32_simd
#define TWIDDLE   ___tc32
#define CFFT_HALF   _cfft16_simd
#elif ( RFFT == 64 )

etc...

It could be great if someone can add here a complete project in ASM, that will compute 1024 point real radix-2 FFT on SHARC (21375 e.g. with using "rfft_simd.asm".

Thanks.

Afi

BF537 Ethernet TXDma Channel Error

analog@sgaur.hosted.jivesoftware.com — Thu, 29 Oct 2009 10:41:08 GMT

Hi,

i have troubles to acknowledge a DMA_Err caused by a EthernetTX transmission.

i use following code derived from original ADI_ETHER_BF537

// ensure a 32 bit access to the MMRs is issued before the 16 bit access in case
// the interrupt killed a 32 bit access - anomaly ED(03-00-0048)
addr = dev->Tx.Dma->START_ADDR;
// check our two DMA channels
if (*pDMA2_IRQ_STATUS&0x02) /*this is the TX int*/
{ // error on TX channel
result = ADI_INT_RESULT_PROCESSED;
// acknowedge the interrupt
*pDMA2_CONFIG &= ~DMAEN;
*pDMA2_IRQ_STATUS = 0x02;
/*dev->Tx.Dma->IRQ_STATUS = 0x02;*/
}

without the red marked line i'm not able to clear the DMA_ERR bit, so i added this one.

( IRQ_status contains 0x03 in my error case)

is this a must or is there any other solution requested?

regards chris

USB daughter board support on 21469??

analog@sgaur.hosted.jivesoftware.com — Tue, 03 Nov 2009 06:15:55 GMT

Hi Guys,

I wonder whether we have support of the USB EZ-Extender support on the 21469 EZ-Kit? I only see Auido Extenders support not the USB EZ-Extender?

If yes, do we have the USB drivers support on the VDSP 5.0 update 6 tools?

Best regards,

Kishore.

Is it definitely a hardware reset?

analog@sgaur.hosted.jivesoftware.com — Wed, 28 Oct 2009 10:42:38 GMT

There is a problem with my BF-533. I suppose that the behaviour can be explained if one assumes that the reset pin is sometimes pulled down for a short period of time. The problem is: I do not know how this could happen (how the pin can be pulled down). Therefore, I would like to know if there are other possible explanations in the following course of events:

Connect VisualDSP++ to the Blackfin Processor via the emulator (HPUSB-ICE)
Load my program to the target.
Read the SWRST register display in VisualDSP++. It says: 0x8000.
Run the program (press the key F5).
The program seems to crash, so I halt the processor (SHIFT + F5).
Read the SWRST register display again. It says: 0x0000.

Does this mean that the reset pin has been pulled down (between steps 3 and 6)? Or are there other valid explanations?

Thank you.

Calculating Filter Coefficients to Store in a Microcontroller

analog@sgaur.hosted.jivesoftware.com — Fri, 20 Nov 2009 20:16:45 GMT

Recently there have been some email support requests regarding the calculation of filter coefficients (and other types of parameters) for storage in a microcontroller. The basic idea is to store a table of parameters in the microcontroller and download them to the appropriate addresses in the SigmaDSP's parameter RAM when required. SigmaStudio includes a few tools to help make this possible.

Method 1: Direct coefficient calculation

This method is not really preferred because it takes time and effort compared to the other methods, and doesn't offer any real benefits. In the help file, equations used for calculating first-order and second-order (biquad) IIR filter coefficients are given. For example, for a butterworth LPF:

These equations can be used to calculate parameters directly, but are a bit cumbersome.

Method 2: Fixed Point Filter Table Generator

Open the fixed point filter table generator under the Tools menu.

Here you can enter in parameters for a number of filter curves that you desire, then hit the generate button to see the generated curves on the graph.

Click the value table tab to see the biquad filter coefficients to be stored in RAM (5 coefficients are listed for each filter generated).

Click the Show Values button and then Generate again to show the decimal values and parameter names for each filter, along with the associated boost.

These values can be loaded directly into a 2nd-order general filter, set to IIR Coefficient mode in SigmaStudio. Important: Because of the way the values are stored in RAM, the coefficients for a1 and a2 must be inverted from what is shown in the filter table generator. The filter table generator shows coefficients as they are stored in RAM, whereas the IIR Coefficient filter box shows their true values as calculated by the equations.

The filter table generator allows a large number of coefficients to be calculated and stored in RAM for applications such as a user-controllable tone control.

Method 3:Use the capture window

Start a project and make sure the SigmaDSP is connected to a USBi communication channel in the Hardware Configuration tab. Insert any filter into your project and compile. Then change the filter values. The values written to the SigmaDSP's RAM are shown in the capture window (open by default, toggle by pressing Ctrl+5).

This allows you to simply generate the parameters for one filter curve.

Figuring out parameters for any SigmaStudio algorithm control using the Capture Window

You can insert any cell into the project, compile, then change its parameters to see what should be stored in RAM in the capture window. If, for example, I wanted to to a sine tone sweep that is manually controlled by a microcontroller, I could enter in a range of values into a sine tone generator and make note of the frequency parameter in the capture window (in this example, the parameter name is sin_lookupAlg19401increment).

Memory problems

analog@sgaur.hosted.jivesoftware.com — Mon, 24 Aug 2009 12:01:53 GMT

Hello,

We're trying to launch our Blackfin prototype (actually we have several of them with same behaviour) and failed in general: both FLASH and SDRAM memory are not working. Read of device code returns 0xDF7D instead of 0x22FD. Please see attached source code - device code is returned with UART0 on 115200. Control byte 0x55 is returned before device code.

RAM also doesn't work. And when we disconnect SDRAM, problem with flash does NOT resolve. So it doesn't look as memory conflict.

We also have ADZS-BF537-EZLITE toolkit and it works. Difference is what we have another memory chips (MT48LC16M16A2BG-75IT, 16MBх16bits) and flash (M29W640FB70ZA6E instead of M29W320DB on kit) on prototype.

Software downloads well. Processor's I/O LEDs functions normally. You can find flash connection scheme in attachment.

Not sure it's helpful information, but there is mark on chip: "ADSP-BF537 BBCZ-5B 124327.1 0.2 #0734 SINGAPORE".

Could you please help with our problem?

how connect data dsp processor to PC?

analog@sgaur.hosted.jivesoftware.com — Fri, 20 Nov 2009 19:18:19 GMT

I make the sound with ADSP 21,369. I wanted to ask how to save the sound of that process into the file. wav on the computer? I use k-lite session to process voice and my 21369th ADSP sharc connect this with the usb port to the computer. how to save a sound process that results in the form of a file. wav for example? help to provide tutorial or program. thanks

List of SigmaStudio blocks ?

analog@sgaur.hosted.jivesoftware.com — Thu, 29 Oct 2009 00:29:49 GMT

Hello,

I am very interested in the SigmaDSP for a specific application (for which it seems a great fit) - however before buying a development kit wanted to check whether there is a full list of SigmaStudio blocks available so that I can confirm that this will support the application - is this available somewhere ?

Paul

Connected Devices Virtual Conference

analog@sgaur.hosted.jivesoftware.com — Wed, 28 Oct 2009 14:32:05 GMT

Hello All:

Just wanted to give you a head's up that EE Times is running a "Virtual Event" Nov 12th. ADI is one of the sponsors for the event and will be participating in three panel sessions. Several ADI members of this forum will also be participating in the webinars. In addition, we will be running some "show specials" for our development tools during this 7 hour conference. Hope to "see" you there.

Rob De

‘Connect Devices’ Virtual Conference

Join ADI at the upcoming virtual conference titled: “Connected Devices, Entering a New Age of Embedded Design,” sponsored by EETimes, on November 12. ADI is a platinum sponsor of the conference and we’ll participate in panel discussions on “Middleware” and “Processors,” and host a one-hour webinar on “Development Platforms for Industrial, Instrumentation and Energy Management Applications.” Our virtual exhibit booth will include training resources, free software downloads, and special discounted offers on development tools. Register now and join us for this virtual event: http://www.eetimes.com/devices/

RAM Check for ADSP21369

analog@sgaur.hosted.jivesoftware.com — Mon, 09 Nov 2009 16:06:04 GMT

Hi,

I am using ADSP21369 in SPI slave mode for booting and therefore my .ldr file is in ASCII format. I want to know the procedure for doing a RAM check of Program memory area.

Is there any way of generate a checksum of any kind in the code image? Any suggestions will be helpful.

Regards,

Syed

Power Consumption between ADAU1701 vs. ADAU1761

analog@sgaur.hosted.jivesoftware.com — Sun, 20 Sep 2009 10:06:45 GMT

Hi SigmaDSP support Team,

what would be the power consumption difference between the ADAU1701 vs. ADAU1761.

1) from the ADAU1701 datasheet, I see that Power dissipation is between 118 ~ 287 mW.

- I am assuming this is mW per hour, correct?

- What would be the most efficient way to use this chipset? Is there a power consumption mode?

2) from the ADAU1761 datasheet, I cannot find any information related except for a description of 10mW on record/playback mode for 1.8V.

- Is this 10mW per hour?

- What would be the most efficient way to use this chipset? is there a power consumption mode?

thank you.

Ron

Problem with upload of code using email response to new entry

analog@sgaur.hosted.jivesoftware.com — Sat, 01 Aug 2009 15:29:34 GMT

I have responded to a new message via the email route rather than loging in toForum

Stream "BF548 Audio signal processing (AD1980 Callback)"

When I checked the displayed uploaded message, many errors were in the code -- in particular many + signs were missing

Also notice the highlighting where * were

I think the issue is that the * in *XYX* are bing interpreted as bold -- I have seen XYX in my emails being received as *XYX* so I think the inverse is happening here

I have also noticed that +XYZ+ changed into XYZ

I uploaded this -- Checked my sent directory records

   #if PLAY_SINE
               *(pDest+(NUM_DAC_CHANNELS*i))    = ReturnNote1( );
               *(pDest+1+(NUM_DAC_CHANNELS*i)) = ReturnNote2( );
#else
               *(pDest+(NUM_DAC_CHANNELS*i))    = *(pSrc+(NUM_ADC_CHANNELS*i));
               *(pDest+1+(NUM_DAC_CHANNELS*i)) = *(pSrc+1+(NUM_ADC_CHANNELS*i));
#endif

but found this on the Forum site after my email was automatically translated

#if PLAY_SINE

(pDest+(NUM_DAC_CHANNELSi)) = ReturnNote1( );

(pDest1(NUM_DAC_CHANNELSi)) = ReturnNote2( );

#else

(pDest+(NUM_DAC_CHANNELSi)) = (pSrc+(NUM_ADC_CHANNELSi));

(pDest1(NUM_DAC_CHANNELSi)) = (pSrc1(NUM_ADC_CHANNELSi));

#endif

NOTE: The change from *XYZ* to XYZ may not be happening at your end but could be something that my email server is doing after I have transmitted the message from my end

Message was edited by: Mike Smith

Problem on TDM Daisy-chain mode ADSP21469 and AD1938

analog@sgaur.hosted.jivesoftware.com — Mon, 26 Oct 2009 08:40:17 GMT

Hello, I am using development board ADSP21469 and development board for AD1938 TDM Daisy-Chain mode with 16-channel DAC. The two chips in question to work on for TDM AD1939 and AD1938. When the DSP, sending 16 channels the same, the system works, but when I send 16 different signals, the system mixes channels 0-8 1-9 2-10 3-11 4-12 5-13 6-14 7-15. I would understand if this anomaly depends on the configuration of the DSP or the configuration of the CODEC. Hello and Thanks

Maurizio

Can I use the ADAU144x as a clock master for an asynchronous clock domain?

analog@sgaur.hosted.jivesoftware.com — Tue, 28 Jul 2009 16:19:49 GMT

Can I use the ADAU144x as a clock master for an asynchronous clock domain?

For example, I have an input data stream that will be a slave to an asynchronous clock domain. I will route it to the ASRCs, SigmaDSP core, back out through the ASRCs and to a serial port. Is it possible to use that serial port in master mode?

Component Weights

analog@sgaur.hosted.jivesoftware.com — Mon, 12 Oct 2009 19:50:44 GMT

Is there a list of component weights with their part number or dscc number?

Thanks!

documentation for windnoise algorithm ?

randyperkins@randyperkins.com — Sun, 04 Oct 2009 05:43:18 GMT

adau144x lists a windnoise algorithm in sigmadsp. I did not see any documentation concerning it except for this circa 2002 article related to the ad1954 .

http://www.analog.com/library/analogDialogue/archives/36-01/sigmaDSP/index.html

thanks in advance

rperkins

Data verification failed at address: 0x800014

analog@sgaur.hosted.jivesoftware.com — Thu, 15 Oct 2009 14:50:42 GMT

I am facing one problem in one of our custom Board. (BF537)

The JTAG is getting connected. But when i am trying to Load my code thru JTAG it displays the following error and i am not able to load my code. The processor is going to IDLE state.

Data verification failed at address: 0x800014
Expected: 0x00, Found: 0x48
Data verification failed at address: 0x1800000
Expected: 0x00, Found: 0x48

This board was working properly before, from today it is displaying this message

Please help us

SPORT Interrupts & FLASH BOOT on ADSP-21364 EZ-KIT LITE

analog@sgaur.hosted.jivesoftware.com — Thu, 08 Oct 2009 15:15:33 GMT

Hy,

I have a problem with interrupts on Sport0, Sport2 and Sport5 that are partially executed.
The program run fine when it is downloaded into the DSP with the VisualDSP++ environment and the EZ-KIT.

All the 3 interrupts generated are executed.
But, when I download the program into the FLASH memory of the EZ-Kit with the driver for FLASH AM29LV081B in way to make the EZ-Kit independent, only the Sport2 interrupt work.

The two others interrupts (SP0 & 5) are not executed.

Those 3 Sports receive at the same time 6 x 32bit words (Channel A & B) and they have the same clk & FS signals that are routed internaly.

When the 3 Sports are full, they generate at the same time 3 interrupts that are executed following their priority. (Sport 5, Sport0 and at last Sport 2).

But only the SP2 interrupt is executed.

I try to configure some registers, but perhaps not the rights...

Here are some lines of some registers:

asm ("bit set LIRPTL BIT_10;") ; //sport0
asm ("bit set LIRPTL BIT_11;") ; //sport2

asm ("bit set IMASK BIT_16;") ; //sport5

I suspect the driver of the FLASH memory to set some registers that are not configured later in my program when it run.

Wich registers do I have to configure in way to be sure to run the interrupts on Sports?

Thanks,

Lorenzo

Sampling & analysing a TV stream in near real time

analog@sgaur.hosted.jivesoftware.com — Sun, 23 Aug 2009 14:02:58 GMT

Hello All,

I’m working on a final year project for college & am hoping somebody can put me in the right direction.

I’m planning to design a consumer electronic device that would sample a TV stream (via SCART in PAL format) & analyse this to detect things such as commercial/ ad breaks in near real time.

I’m completely new to the video capture area but I’ve been looking at the ADV7441A chip & then possibly passing this onto a Blackfin chip for the DSP side of the application.

I’m unsure of

Is this application possible/ realistic
What the best video format for analysis would be
How to analyse the captured video
The processing power to analyse this in near real time

I’d appreciate any input/ suggestions as to the best method of implementing the solution.

Regards,

Leo738

What's the proper way of using VDK messages?

yair@raztek-inc.com — Fri, 25 Sep 2009 03:23:01 GMT

In several examples (both in the VisualDSP install, and online training module), I've seen examples that reuse VDK messages, e.g.:

Thread1 creates messages at init time, and send them on a channel to thread2. Thread2 reads them, and send them back to thread1, which reuses them.

What is the tradeoffs between this method, and the simple (and logical method of):

- Thread1 creates a message when needed, and sends to thread2

- Thread2 pends on a message, and when receives is, gets its payload and then destroys it.

Obviously, method 2 is much easier to implement.

What method is to be used when writing complex applications?

Regards,

Yair

adsp2136x spi full duplex capability

analog@sgaur.hosted.jivesoftware.com — Thu, 05 Nov 2009 23:42:07 GMT

All,

I am using an adsp21364 tied to a serial flash module. In order to read data from this module I must first transmit a command word over SPI. Easy enough.

The problem is that the flash module begins transmitting the first bit of the requested data immediately after receiving the command. My question is if the only way to initiate full duplex communication via SPI is to utilize DMA transfer for receive?

Or can I immediately reconfigure the SPICTL (without disabling SPI) register to initiate a master core receive fast enough to be able to capture the data the flash module is transmitting?

Thanks much.

Compiler conditional compile option for simulator

analog@sgaur.hosted.jivesoftware.com — Mon, 09 Nov 2009 05:23:17 GMT

The compiler allows conditional compiles using

#if defined(__ADSPBF533__) etc so can select between code for various compilers

When you switch over to a simulator session, you often need to change loop sizes so the simulation completes in a reasonable amount of time

if there a conditional compile setting best on "session"

#if defined (__SIMULATOR_SESSION__)

Thanks

Automatic Gain Control

analog@sgaur.hosted.jivesoftware.com — Sun, 08 Nov 2009 12:14:40 GMT

Hi i'm new to the world of DSP and i'm using the ADAU1701 is it possible to create a automatic gain control.

if so how do i start?

Auto logout and tab preferences

analog@sgaur.hosted.jivesoftware.com — Sat, 29 Aug 2009 12:41:16 GMT

Hi,

A couple of questions:

1. Why an I being automatically logged out after a short time of inactivity? How can I change this preference?

2. When opening a forum I get the Overview tab as the default although I set the Discussions tab as a default (after opening it, of course). Why isn't my selection saved?

Thanks,

Yaniv.

Getting I/O data using DMA

analog@sgaur.hosted.jivesoftware.com — Fri, 23 Oct 2009 18:37:58 GMT

Hi folks,

I'm new working with Analog Device processors; I'm with a SHARC DSP and I have a newbie question:

I have to get parallel data from an ADC with a frequency of 16MHz. Can I program some I/O pins of the SHARC processor with DMA at that frequency? Or DMA can only be used for communication ports such as SPI and serial UART?

Thanks for your attention,

Pedro.

Matrix Multiplication in TS201

analog@sgaur.hosted.jivesoftware.com — Tue, 06 Oct 2009 07:22:04 GMT

Iam trying to use the In-built function cmatmmltf matrix multiplication in TS201

I need to pass the matix values from memory (tiger sharc internal memory) and perform

matrix multiplication and result should be stored in memory

The code is shown below

#include <Tigersharc.h>
#include <signal.h>
#include <matrix.h>

void main()

{
    const complex_float *a = (complex_float *) 0x140000; /* Pointer to input matrix a[][] */
    int n = 2; /* Number of rows in matrix a[][] */
    int k =2; /* Number of columns in matrix a[][] */
    const complex_float *b = (complex_float *) 0x140004;; /* Pointer to input matrix b[][] */
    int m = 2; /* Number of columns in matrix b[][] */
    complex_float *c = (complex_float *) 0x140008; /* Pointer to matrix c[][] */

cmatmmltf (a,n,k,b,m,c);

}

I need to pass a[2][2] = {1.0 1.0 and b[2][2] = { 1.0 1.0

1.0 1.0 } 1.0 1.0 }

Is the above method of using the matrix function is correct ? Becaz Iam not getting the expected result at 0x140008

Mahendran

Blackfin ezkit/stamp Altium files

analog@sgaur.hosted.jivesoftware.com — Mon, 26 Oct 2009 07:48:07 GMT

Hey,

I was wondering if the Blackfin ezkit or stamp boards had altium/protel files available to assist with development? I would like to use the same dsp/ram/flash set-up as well as power/caps etc. It would definately improve the chances of the board working out..

thanks..

p.s. does anyone know of a PCBA place that would solder up bga components on a one-off/prototype basis (and not cost a fortune). This is appearing to be our biggest barrier from getting something off the ezkit...

PLL on ADSP21371

analog@sgaur.hosted.jivesoftware.com — Wed, 04 Nov 2009 11:36:58 GMT

Hi to all

I want to use the PLL to configure the core clock.in the examples of code i saw that the PLL has to be placed in bypass mode and after that its cleared of the bypass mode. Why it should be placed in this mode?

Receiving Data using SPORT DMA

analog@sgaur.hosted.jivesoftware.com — Fri, 02 Oct 2009 12:43:03 GMT

Hello,

I have an external device generating a waveform that I want to read (hopefully using the SPORT DMA). The external data has a start bit when the data is generated by the external device. The waveform only lasts 546 usec and repeats at intervals of 800 usecs. The external signal is low after the waveform is sent for 253 usec. There is no clock and no frame sync from the external device.

How will the SPORT know when to start reading the data at the start bit every 800 usecs? I am afraid it will start reading in the middle of the signal. Can I even use a sport since there is no synchronization?

lwIP porting and SNMP protocol

analog@sgaur.hosted.jivesoftware.com — Fri, 02 Oct 2009 13:58:37 GMT

If I'm right lwIP supports also SNMP protocol, but does the blackfin porting (with VDK) support this protocol?

In the TCPIP Configuration Window I can enable only TCP, UDP, ICMP and DHCP.

Is there a working example with SNMP protocol, VDK and blackfin?

- vix

Using VisualDSP++ 5.0 Update 6

testing bits

analog@sgaur.hosted.jivesoftware.com — Wed, 29 Jul 2009 07:34:48 GMT

i am working on ADSP-TS201

is there a predifined macro that can help me in testing if a certain bit is high or low in a certain register because i make it with two command lines and i use this syntax alot and to use this indication in for or while loops

thank you for your time

new interrupt function and interrupt vector table

analog@sgaur.hosted.jivesoftware.com — Tue, 23 Jun 2009 17:52:39 GMT

Hello,

I have a new interrupt function that I wish to attach to my application. It's a Timer interrupt.

I'm setting it up using the timer_set and attaching it to SIGTIMER as follows

if (timer_set(0x1000,0x1000,0) != 1)

{

interrupt(SIGTIMER, Timer_ISR);

timer_on();

}

I have also modified the interrupt vector table to use the new Timer_ISR function as follows

.SECTION/PM IVtimer;

.global ___tmri;

___tmri;

ena sec_reg;

jump _Timer_ISR;

rti;

___tmri.END;

During execution/debuggin, the Timer_ISR is either executed a single time or the application enter a strange state and the ICE can't communicate with the device and I have to reset the system.

VDSP Issues with Vista

analog@sgaur.hosted.jivesoftware.com — Thu, 29 Oct 2009 09:56:20 GMT

Hi guys!

Does the VDSP++ 4.5 IDDE have issues with the Windows Vista Home Premium Edition? Any piece of information from you guys will do and will be greatly appreciated.

Regards,

Allan

SigmaDSP FAQs?

analog@sgaur.hosted.jivesoftware.com — Tue, 20 Oct 2009 13:22:13 GMT

Where can I find a list of SigmaDSP and SigmaStudio FAQs?

ADSP-2101 Emulator help needed

analog@sgaur.hosted.jivesoftware.com — Fri, 28 Aug 2009 19:52:35 GMT

I am using this old legacy emulator since i need to update old products but i am having a few issues...

Issue1 Boot images: The code I am using loads up to 6 different boot images depending on the hardware being used. My init routine will setup the DSP then at the end program decides which image to load from external ROM, resets the chip and does a while(1) until the chip resets and loads the correct code. I am trying to figure out how to use the emulator effectively. I would like to load the init code and execute to the end with loading any boot images, then load the main code but cannot seem to do this since the emulator complains about code being loaded over its 0x7ff internal program memory limit. Each boot image is located above the 0x7ff address. See below on my next step on trying to debug...

Issue2 Breakpoints: I put in the external prom and reset the emulator and it runs the code correctly by loading out of the external prom. I can stop the emulator and set breakpoints. Then i run the emulator again and restart the code but the emulator will never stop at any breakpoint. I stop the emulator and indeed the breakpoints are still there. The only thing i have noticed is to zero out the IMASK register, then breakpoints are hit but this disables all my interrupts.

Issue3 Manual: Is there an emualtor manual for the 2101 EZ-kit. I cannot find this except for a few page datasheet on EZ-kits for the family.

thanks

Can we bundle SigmaStudio with our product design?

analog@sgaur.hosted.jivesoftware.com — Thu, 10 Sep 2009 13:52:46 GMT

We are designing an audio system using a SigmaDSP as the processor. Can we provide SigmaStudio to our end customers as a tuning tool to interface to our product?

complier`s problem with the option of -char-size-8

analog@sgaur.hosted.jivesoftware.com — Mon, 31 Aug 2009 08:58:17 GMT

Hello, the complier exist the bug when the option of "-char-size-8" is available.

processor : TS201

tool : VisualDSP++ 4.5 (product:4.5.0.0 IDDE: 7.0.0.0, build: may 4, 2006)

example code:

char *pText = "abcd"; /* pText = 0x0008597C */

char *pCur = pText; /* pCur = 0x0008597C */

pCur++; /* pCur = 0x4008597C */

pCur++; /* pCur = 0x8008597C */

int nLen = pCur - pText; /* nLen = 80000000 */

the expected result of nLen is 2, but......????

Make Plot

analog@sgaur.hosted.jivesoftware.com — Wed, 04 Nov 2009 11:20:49 GMT

How to find data memory / program memory to the plot? Because so many choices. Please help

Developing VisualAudio Modules

analog@sgaur.hosted.jivesoftware.com — Fri, 25 Sep 2009 16:13:30 GMT

Where can I find information describing how to develop VisualAudio modules?

I downloaded the Standalone VisualAudio Modules. I wanted to modify the FIR routine to do decimation. In reading the VisualAudio Module Usage Guide, it says for more information on creating modules to refer to "Developing VisualAudio Modules". I've been unsuccessful in locating such a document in the documentation that was downloaded with the modules, nor on the ADI website. The manual that has the reference is attached.

Thanks,

David

Surround Sound Volume Control, what does it do ?

randyperkins@randyperkins.com — Mon, 05 Oct 2009 06:06:45 GMT

Hello

the 144x includes a "Surround Sound Volume Control" on SigmaStudio. The documentation states

"The Surround Sound Volume Control block enables positioning of source elements relative to a listener head."

Forgive me for my lack of understanding, but I am wondering what it does. I was hoping it added small amounts of delay to the speakers that were positioned closer to the listeners head, in order to improve imaging (phasing). However I created a very large room and positioned the speakers to require the maximum delay, but when I compiled the program, it doesnt seem enough resources are reserved to accommodate the necessary delay.

I'm assuming it takes 1ms of delay for each foot of distance per speaker that said speaker is closer to the 'sweet spot'(head) than the furthest speaker.

also this 'volume control' doesnt have any "knob' on it, so I'm confused if it makes gain adjustments.

on a related note I think

the readme included with the application mentions "enhancements for SigmaStudio3.1.8".

The one I am interested in is "beta version of phase response for transfer function window using probe/stimuli"

My limited understanding is an analog 3rd order buttersworth filter is neutral to the phase but that most other manipulations of the audio shift the phase of the output

ultimately I want the appropriate delay (per speaker) either manually programmed into my application, or to be computed with the aid of a mic input.

also if the dsp shifts the phase of an input signal, I'd like to account for that also. this is all to improve the imaging of the output to the primary listener at the sweat spot.

thanks for your patience with me.

rperkins

the autosave feature on this forum software moves my curser as I try to type . firefox 3.0.14 , ubuntu

BF561 & JPEG - to convert analog video to digital

analog@sgaur.hosted.jivesoftware.com — Tue, 29 Sep 2009 17:00:23 GMT

I am using the ADSP-BF561 EZKit

I would greatly appreciate any assistance I can get. Currently, I participate in an ongoing hobbyist project. We have remote analog video working wonderfully and would like to convert the analog video to digital to maximize distance and video clarity.

My first goal is to prove that the Blackfin 561 can sample a frame of video on CoreA and encode it to JPEG then CoreB decodes the JPEG buffer and sends a frame of video out the PPI to be displayed. I understand this approach is not optimized for bandwidth but, I need to get as close to realtime video (no perception of delay) as possible. Reaching the first goal will demonstrate that the Blackfin 561 is capable of the task and I believe it is. A future design can be adapted to transmit packetize video via 802.n but, only if the first stage is possible.

I downloaded and have been working with the JPEG_Encoder Rel 3.1.1 for weeks now in my spare time with no progress. Using the example code and documentation has left me confused about how the library is designed to function. While it seems very straightforward still, I cannot get it to work – that is, encode a frame of sampled video.

I know there are other possible solutions for this project but, I prefer using the blackfin – If I can make it work. H.264 has been a consideration but, I cannot find out how many frames of delay it introduces. This digital video process may sacrifice bandwidth for any delay introduced by the encoding/decoding process. (2-4 frames behind is tolerable)

Does anyone have any working sample code that you wouldn’t mind sharing with me? I have a strong desire to learn and it is the reason I participate in hobby projects.

voice recognition with ADSP 21369 sharc

analog@sgaur.hosted.jivesoftware.com — Sun, 11 Oct 2009 16:01:42 GMT

My final task was set to S1. Theme of my final task is the implementation of voice recognition with ADSP 21369 sharc. If I may ask for the knowledge-knowledge of coding in the visual dsp + + for voice recognition. thanks

help me.

How can I calculate the value series termination resistors?

analog@sgaur.hosted.jivesoftware.com — Wed, 08 Apr 2009 20:39:55 GMT

How can I calculate the value series termination resistors? How accurately can the resistance value be calculated. Are 1% resistors required?

c code for uart transmission and recepiton in dma mode through interrupt for blackfin bf533 interfaced with gsm/gprs modem

analog@sgaur.hosted.jivesoftware.com — Sat, 03 Oct 2009 07:20:49 GMT

I am new to blackfin bf533 processor.i would like to interface the sim enabled gsm/gprs modem interfaced to bf533 and write a code for the transmissioon of at commands through uart to modem and reception of modem response through uart in interrupt dma mode.if any one have the c code please help me out

thanks

regards

balaji

Is there a cross ref chart listing the available parameter, program and data ram for all sigmaDSP processors ?

randyperkins@randyperkins.com — Sat, 03 Oct 2009 19:56:23 GMT

for example:

I believe the 1701 has 3k of parameter ram, 4k of program ram, and 2k of data ram.

Is there a chart that compares this info for all SigmaDSP processors ?

or do I need to review the data sheet for each processor

I could be way off but do think this would be great information to include on the selection tables here:

http://www.analog.com/en/embedded-processing-dsp/sigmadsp/processors/index.html#Audio_Signal_Processors

thanks

rperkins

im thinking the number of control registers usable for saved parameters would be usefull also.

IE: i think the 1701 has 8 registers.

verifying the clock rate of ADSP-TS201

analog@sgaur.hosted.jivesoftware.com — Mon, 27 Jul 2009 12:57:15 GMT

hello

i am working on ADSP-TS201 and i was developing a program to train my self on delay programs and my calculatios was made so that the clock is 600 MHZ so the timer clock will be 300 MHZ and when i tried to measure the time for which the delay program works it gives me that delay was for 1,2 sec althogh

my calculations are made so that it should be 1 sec and what i think is that we ordered a worng processor so please see the syntax i made and tell me if i am right or wrong

/*****************************************************************************
* delay_testing.c
*****************************************************************************/
#include<sysreg.h> // header file to define the various registers in the ADSP-TS201
#include<math.h> // header file to use variuos math operations
#include<stdio.h>
#include<defts201.h> // header file to define the bits and registers numbers to be used directly
#include<builtins.h>
#include<time.h>

#define SYSREG_CLR(sysreg,bit) __builtin_sysreg_write(sysreg, __builtin_sysreg_read(sysreg)&~bit) //macro used to clear the bits
#define SYSREG_SET(sysreg,bit) __builtin_sysreg_write(sysreg, __builtin_sysreg_read(sysreg)|bit) //macro used to set bits

void delay(void)
{
unsigned int x;

    SYSREG_CLR(__INTCTL,INTCTL_TMR1RN);

    SYSREG_SET(__SQCTL,SQCTL_GIE);

    __builtin_sysreg_write(__TMRIN1H,0x00000000);
    __builtin_sysreg_write(__TMRIN1L,300000000);

    SYSREG_SET(__INTCTL,INTCTL_TMR1RN);

    x= __builtin_sysreg_read(__ILATL);
    x&= INT_TIMER1L;

    for(;x!=8;)
    {
     x= __builtin_sysreg_read(__ILATL);
     x&= INT_TIMER1L;
    }

    __builtin_sysreg_write(__ILATCLL,0x0);


}

int main(void)
{
volatile clock_t start;
volatile clock_t stop;
float seconds;

printf("one\n");
start=clock();
delay();
stop=clock();
printf("two\n");
delay();
printf("three\n");
delay();
printf("four\n");
delay();

seconds=((float)(stop-start))/CLOCKS_PER_SEC;

printf("seconds= %f\n",seconds);
return(0);

}

and the output was okay and there was the delay i made but the period of the delay (seconds ) was not correct so i changed the value loaded to the timer to be (250000000) and then the delay was 1 secs so is that veryfies what i am saying is that the processor is 500 MHZ and not 600MHZ as we ordered it

the output was;

one
two
three
four
seconds= 1.200000

Interaction between SPI and FLAGS?

analog@sgaur.hosted.jivesoftware.com — Sat, 24 Oct 2009 23:52:09 GMT

I am using the SPI port in my program for the ADSP21369,

and I also use FLG0 through FLG3 for diagnostic output. I have

found that when I try to write to the FLAGS register close to

where I use SPI communications in my program, the processor can hang.

It says in the manual that if you disable the SPI port by setting

a bit in the PMCTL register, you can't use the FLAGS because

they are "synchronized to the clock." I must admit that I have

no idea what that means. I don't write to the PMCTL

by writing zeros to the SPI control registers. But still there seems

to be a definite interaction between using SPI and changing flags

by writing to the FLAGS register, and as I mentioned it can

crash the program. Does anyone understand the nature of this

interaction? Is it documented anywhere? I really don't understand

the brief allusions to it in the Hardware Reference Manual and

the Programmers Reference manual.

Thanks,

Richard

Why I cannot use the stadnalone debug agent to debug all Blackfin and Sharc processors

analog@sgaur.hosted.jivesoftware.com — Wed, 21 Oct 2009 11:30:09 GMT

The price of USB-Based Emulator and High Performance USB-Based Emulator is very high. The price of Standalone Debug Agent isa very democratic/ But I cann't to use him in my target boards? The emulator for all TI's processors is very low шn comparison AD's emulators? Why?

Why a policy on distribution of a product less flexible than at the competitor

Regarding DAC 32 Channel,14 bit Parallel input, (0-10)V Analog output

analog@sgaur.hosted.jivesoftware.com — Fri, 31 Jul 2009 12:03:33 GMT

Hi,

I am having design requirement with DAC 32 Channel,14 bit Parallel input, (0-10)V Analog output. I have seen in your product list. But, i couldn't find Digital to Analog converter chip for DAC 32 Channel,14 bit Parallel input, (0-10)V Analog output. If that is there, please send it to me by immediately or suggest that part number. It is urgent requirements.

Please reply me as soon as possible.

Thanks and Regards,

N.Magalingam

Hardware Design Engineer-Embedded System

Cornet Technology India Pvt Ltd

Chennai-20

Mobile:+91-9994867369

Data Bus Selection

analog@sgaur.hosted.jivesoftware.com — Fri, 30 Oct 2009 10:59:50 GMT

Hi All,

With reference to my earlier post, wherein I am using ADSP-TS201S with an auxiliary FPGA Cyclone-II, I have an additional question

For SDRAM and FLASH, I am sharing the data bus (D0-D31) of the DSP processor. Now for other peripherals present on my board, the maximum data-width required is 32. And this data-bus is being used to interface via Cyclone-II FPGA i.e. the data path is

ADSP-TS201S -> Cyclone II FPGA -> PERIPHERALS

I am confused as to whether I should use D0-D31 (the same bus used for SDRAM and FLASH) for these peripherals or whether I should use D32-D63 (higher word) data bus. What advantages/disadvantages could I have in either case?

Thanks and Regards,

Sid

ADAU1401 IIS connection problem---- how to deal with the four channel IIS serial data input to ADAU1401

analog@sgaur.hosted.jivesoftware.com — Fri, 09 Oct 2009 03:20:28 GMT

If I have four channel I2S serial data input to ADAU1401 , how should I deal with the INPUT_LRCLK & INPUT_BCLK Pin ? Because I have 4 pair of LRCLK&BCLK ,but ADAU1401 only one pair of LRCLK&BCLK.

How do I design a self-boot system?

analog@sgaur.hosted.jivesoftware.com — Tue, 28 Jul 2009 16:28:47 GMT

How do I design a self-boot system?

AD1445 multipurpose pins driven by control port

analog@sgaur.hosted.jivesoftware.com — Fri, 09 Oct 2009 00:05:38 GMT

Hi,

On AD1445, we want to use some of the multipurpose pins as digital output pins, and we want them driven by the control port, i.e. the I2C interface. To control those outputs, the datasheet says (Rev A, page 67) we can read/write the addresses listed in Table 64, but what's confusing me is Table 64 is just a list of control registers used for pin modes selection. Also, those registers are 16-bit, you can't read/write 5.23 formatted data from/to them as mentioned in the datasheet. I guess it's referring to some other addresses, but where? Thank you.

Regards,

Rong

Expert Linker Post-Link not working

analog@sgaur.hosted.jivesoftware.com — Fri, 23 Oct 2009 08:27:11 GMT

Hi,

I'm using VisualDSP++ 5.0 update 6 together with a SHARC dsp and in the Expert Linker I cannot use the option Post-Link in View / Link Results (Post-Link). That used to work in version 4.0...

I confirm that the PROJECT_NAME.map.xml file was generated correctly and I can open it in IE without problems. It's just much more difficult to go through the xml file instead of using the Expert Linker.

Is this a known issue? Any clue about what is causing it?

Thanks,

daniloz

Is there a way to push data into the TS201 memory via the IDE?

analog@sgaur.hosted.jivesoftware.com — Tue, 28 Jul 2009 16:41:55 GMT

I am new to TS201 development and am trying to test an algorithm which we have ported to the TS201. I would like

to pump data blocks (~8k of integers) into our algorithm and have it process the data. I don't mind setting break points

and manually updating a specific memory location with the data to process, but it's obviously not viable to manually enter

this much data by hand. So, have I overlooked a mechanism which exists for writing data to the DSP? I prefer to not

have to develop any additional interfaces.

TIA for any suggestions.

greg

VDSP .ldf Regeneration

analog@sgaur.hosted.jivesoftware.com — Tue, 20 Oct 2009 19:47:50 GMT

I'm working with VDSP 5.0 Update 6, and BF527 EZKit. We have a project which was created using the
wizard to create an .ldf file for us. This means any time Project Options are changed VDSP will
regenerate the .ldf file. This is a problem for us. We have made custom changes of our own to
the .ldf file which we don't want overwritten. Most of our custom changes can be protected by enclosing
them in the special comments:

/*$VDSG<insert-new-memory-segments> */
/* Text inserted between these $VDSG comments will be preserved */
/*$VDSG<insert-new-memory-segments> */

However some of our changes cannot be protected with the special comments. For example:
We replace:
MEM_SDRAM0_BANK3 { TYPE(RAM) START(0x03000000) END(0x03ffffff) WIDTH(8) }
with:
MEM_SDRAM0_BANK3 { TYPE(RAM) START(0x03000000) END(0x03ffBfff) WIDTH(8) }

We place our new definition of MEM_SDRAM0_BANK3 inside the special comments and
comment out the old defintion. BUT every time VDSP regenerates the .ldf it replaces the
old definition leading to a redefinition of MEM_SDRAM0_BANK3 and giving build errors.

Questions:
1.)How can we turn off VDSP's .ldf regeneration?
2.)Why does VDSP regenerate the .ldf? Is there some benefit to the regeneration?
We need to know exactly what VDSP changes in the .ldf when it regenerates.

Which VisualDSP++ Updates do I need to install?

analog@sgaur.hosted.jivesoftware.com — Fri, 16 Jan 2009 19:01:39 GMT

The VisualDSP++ Tools Upgrades page lists several updates. Do I need to install them all in order? Why are some listed and not others?

What is the best way to change a timer frequency without stopping the timer

analog@sgaur.hosted.jivesoftware.com — Wed, 14 Oct 2009 16:03:09 GMT

I start out using a timer set to interrupt at 70 Hz. Then I want to adjust the timer interrupt to another value around 70 like 69.5Hz. My timer will need to adjust as a function of a commutator speed. I cannot stop the timer. Can I adjust TM0PRD while it is running?

Thanks,

Filter and FFT functions

analog@sgaur.hosted.jivesoftware.com — Sun, 16 Aug 2009 04:13:52 GMT

Hi,

I'm trying to use the filter and fft functions (listed in the filter.h file).

fir_fr16 and rfft_fr16 are the ones giving me problems at the moment.

I'm very confused about the syntax, and how to use the functions themselves.

Could somebody please help me out with this?

Specifically: How do you define the inputs: if I have data coming in, I can't define it at type "const", because it needs to be a variable.

Also, the help file lists:

fir

#typedef struct

# fract16 *h, /* filter coefficients */

# fract16 *d, /* start of delay line */

# fract16 *p, /* read/write pointer */

# int k; /* number of coefficients */

# int l; /* interpolation/decimation index */

#} fir_state_fr16;

whilst the header file lists:

typedef struct
{
    fract16 *h;    /* filter coefficients            */
    fract16 *d;    /* start of delay line            */
    fract16 *p;    /* read/write pointer             */
    int k;         /* number of coefficients         */
    int l;         /* interpolation/decimation index */
} _fir_fr16_state;

As you can see, these two are differently named.

This is just for fir_fr16. I also need to be able to use fft's and ifft's, so if anybody can help me out with those too, I'd much appreciate it.

I'm completely lost as to what need to be input/output to make these functions work.

Analog Circuits forum

analog@sgaur.hosted.jivesoftware.com — Tue, 23 Jun 2009 16:09:44 GMT

I would like to see the forum expanded to include other ADI products like Amplifiers and Converters (ADCs and DACs) and RF. Everything would be nice.

If you do too, please post it here

Will adding zeroes to FIR filter coefficients to increase taps degrade performance?

analog@sgaur.hosted.jivesoftware.com — Wed, 21 Jan 2009 15:56:14 GMT

We have two FIR Filters, running on same input data, generated for different
purposes.

1. FIR1 - N Taps (as generated in Matlab)
2. FIR2 - N+10 Taps (as generated in Matlab)

Case 1
======
Have 2 separate Input Data Arrays of length matching to the taps.
i.e.
Array 1 of length N for FIR1.
Array 2 of length N+10 for FIR2.
Feed the incoming input sample to both the arrays.

Case 2
======
Have a single Input Data Array of length N+10.
i.e.
Array of length N+10 for both FIR1 & FIR2.
Feed the incoming input sample to the array.
Add 5 zeroes on each side of the filter coefficients for FIR1 to make it length
/ taps as N+10.
i.e.
FIR1 = [0, 0, 0, 0, 0, N Original Generated Coefficients, 0, 0, 0, 0, 0]
FIR2 = [N+10 Original Generated Coefficients]

"Case 1" brings in complexity in our design and hence we were looking into
"Case 2" and have certain queries:
1. Will adding zeroes degrade the performance of the filter i.e. roll-off/
attenuation etc. ?
2. Will the group delay of the Filter(original generated with added zeroes)
differ from the Filter(original generated coefficients) ?

Kaushal

why readback only in 24.0 format?

analog@sgaur.hosted.jivesoftware.com — Thu, 20 Aug 2009 07:33:39 GMT

Why is it not possible to readback values in 28.0 format? I think this would be very useful!!!

For example I would like to monitor the value that is fed to a index selected mux. As far as I can see this input is in 28.0 format. When I use the readback cell I can only select 24.0 format as a maximum. So I always see 0.0000000.

A similar problem is monitoring te AUX ADC value. Here I'd like to monitor the value to calculate the divider that is needed to feed a lookuptable which in turn feeds a "sigle slew ext vol". This is to control volume with predefined steps and range using an ext. pot.

Regards

Bernd

SPI SLAVE BOOTING on 21371

analog@sgaur.hosted.jivesoftware.com — Mon, 19 Oct 2009 09:44:19 GMT

Hi,

in SPI Slave booting from a host procesor, do i have to use DMA when transmiting data to DSP21371?

ADG794 video switching

analog@sgaur.hosted.jivesoftware.com — Thu, 20 Aug 2009 07:18:44 GMT

Has anyone had success with this chip?

I'm experiencing really bad crosstalk between the two inputs. input 2 audio coming through to input 1 side.

Can anyone help on this?

The video is perfect... just the audio that's causing a problem!

Booting and DDR memory configuration on BF548M

analog@sgaur.hosted.jivesoftware.com — Wed, 28 Oct 2009 08:37:26 GMT

I am having issues with correct initialisation of the BF548M DDR controller when the system heap user heap and stack are in L3 memory. To start with there seems to be no documentation or examples of how the controller registers should be set up for Mobile DDR. By looking through the defines is some of the header files I found that there is an extra bit (bit 5) in the EBIU reset control register that need to be set. This is undocumented. The problem is when to set this bit. I have found that I have to have separate initialisation code for getting the processor to load from SPI Flash. This does not get run when developing code and down loading it through the emulator. How and where should I put this initialisation in my main code. I think it should be built in to the default initialisation for the processor, but there does not seem to be any difference between the BF548 and the BF548M. Have the tools not kept up with the hardware? I am not sure if I have described the problem very well but some insight into how to use L3 memory with the BF548 would be apreciated.

I also have a side issue with VDSP++ with removing startup code and LDF. Once introduced into a project it seems imposible to remove it again without deleting the porject and starting again. As anyone a cure for this?

BF561+PCI

analog@sgaur.hosted.jivesoftware.com — Mon, 12 Oct 2009 09:52:34 GMT

Hi all,

Do you have any reference design/solution for adding a PCI interface (like PCI9054) to BF561 or other Blackfin except BF535?

Thanks for your sharing.

Reposted -- Simulator and watchpoint registers and ssync( )

analog@sgaur.hosted.jivesoftware.com — Mon, 12 Oct 2009 14:50:39 GMT

I am reposting this as the original thread ended up marked "answered" and thats an action that can't be undone

I have some exceptions associated with the instruction watch debugger that I need to analyse -- there are a couple ofpipleine hits that I am not expecting and I wanted to see if I could hand code the exceptions.

Trouble was -- I could get the instruction watch exceptions to activate in real life but not on the simulator.

Do either of the Blackfin simulators support the instruction watch or data watch operations?

If not, I will trigger the exception routines a different way and use the pipeline viewer then, but would be nice not to have to.

I then thought I had got into the instruction watch exception by "running" the simulator "for a long time", but it turned out that there was another problem that threw the exception.

Although I could not recover from what every exception the simulator thought had happened (in the same way that the real processor had recovered) , the fact that I got to the exception

enabled me to do the analysis on the timing of the exceptions and left me with two questions

Alot of the exception time was associated with the ssync( ) instruction which ended up being tranlated as cli r0; ssync, sei R0, which allows the ssync to proceed without being interrupted

Q1A -- should all ssync csync be treated the same way?

Q1B -- IS that process unnecessary in an exception since exceptions can't be interrupts?

Q2 Do the simulators support instruction watch operations and I did not managed to do something correctly?

Thanks

Mike SMith

ADAU1761 Boot-Loader

analog@sgaur.hosted.jivesoftware.com — Tue, 27 Oct 2009 15:10:50 GMT

So, I've been using the ADAU1761 Eval Board and it's working out great for us! We're starting to design our own circuit and are running into some questions about loading the program at boot time. With the ADAU1761, we have to use a uC/EEPROM to load the program at boot. Any suggestions for uC? Will a PIC/PICAXE work? Any examples out there? We're thinking of using a microSD flash card instead of EEPROM chip, so that we can send our users new programs and they can load them on their own using the microSD. Any concerns there?

Thanks!

--> freddie

Software reset on ADSP-21369

analog@sgaur.hosted.jivesoftware.com — Thu, 05 Nov 2009 20:03:52 GMT

Hello,

I've the following problem with the ADSP-21369 (I'm using the EZ-KIT 21369 together with VisualDSP 5):

I want to reset my DSP completely so that the execution of the programs start exactly like it would after a boot: stack cleared, all variables should be reinitializated and all peripherals (SDRAM-controller, SPORT etc.) should be resetted, just like when I toggle the reset line. But I want to do that via the program itself without asserting the reset pin from the outside.

I already found out that I can perform a software reset via setting bit 0 in the SYSCTL register. But that does not work. The DSP restarts (I can verify that with turning on/off the LEDs on the eval-board) but the sound output is disturbed then (the sound is overlayed with a crackling then, but you can hear a little bit the expected sound).

I already tried a hard coded jump back to the memory address where the init code is placed by the linker. No success same problem.

Interestingly I can reproduce the problem if I connect to the board via VisualDSP, run the program and press the reset button. The execution does stop then on the breakpoint on the first line in main() like it always does but if I press then F5 it goes wrong (again crackling) while it worked fine for the first run before I press the reset button.

And the crackling already occurs after the reset without having started the SPORTs so in fact the DSP does not send data at that moment.

Next interesting point: When I put the program into the SPI falsh and run it from there standalone (having VisualDSP disconnected) it runs fine and I can press the reset button as often as I want without crackling.

Any ideas?

Raphael

how to connect SHARC to host controller

analog@sgaur.hosted.jivesoftware.com — Thu, 29 Oct 2009 02:11:56 GMT

Hi,Guys,

My customer wants to use SHARC(ADSP2136X or ADSP2146X) as co-processor, and use PowerPC as host. They want to use host-slave parallel port to connect 2 chips directly. I could not found HDMA or HPI interface on SHARC. Is there any other parallel port which could support host control, instead of using dual-port RAM between host controller and SHARC external memory interface?

Thank you

hi all, I have problems with ade 7753

analog@sgaur.hosted.jivesoftware.com — Tue, 23 Jun 2009 22:10:17 GMT

quien me puede ayudar con el ADE 7753?

ADSP21371

analog@sgaur.hosted.jivesoftware.com — Wed, 14 Oct 2009 20:25:51 GMT

Hi to all

i want to know in wich version of VisualDSP++ there is more examples for ADSP21371? I am using now VisualDSP++5.0 - is there newwer version with more examples??

How to use a single chip microcomputer control filter?

analog@sgaur.hosted.jivesoftware.com — Sun, 20 Sep 2009 05:47:18 GMT

Hello!

I use ADAU1446,in the SigmaStudio's Crossover module,i found there are different numbers addresses is shown in the Capture window when i select different filter.
For example,when i choose Butterworth 12 ,there are 5 addresses,and Bessel 24,there aer 10 addresses.I can't found which Coefficients match with these addresses,and
how to compute them.

Can you provide me the detailed algorithm just like General 2nd-Order Filters algorithm.Thanks!

Are EZ-KIT Lite schematics available on the web?

analog@sgaur.hosted.jivesoftware.com — Wed, 18 Feb 2009 09:51:36 GMT

Are EZ-KIT Lite schematics available on the web?

Adding and subtracting 0x80000 in Chain pointer register

analog@sgaur.hosted.jivesoftware.com — Wed, 15 Apr 2009 20:54:59 GMT

In the Talk Through example in VisualDsp++, I see the following piece of code, while initializing the chain pointer register, in the initSPORT section,

TCB_Block_A[0] = (int) TCB_Block_C + 3 - OFFSET + PCI ;

Both OFFSET and PCI have value of 0x80000, why is added and subtracted?

REQUIRE : Visual DSP++ 5.0 Update 3 or higher

analog@sgaur.hosted.jivesoftware.com — Fri, 02 Oct 2009 10:03:04 GMT

HI
I am having Visual DSP++ 5.0 but for installation it is requiring an Update 3 or higher which is 314MB on net and I am unable to download
Can you PLEASE help me

Thanks

VDSP tool version that can be used for development with ALL DSP Processors from Analog Devices

analog@sgaur.hosted.jivesoftware.com — Wed, 16 Sep 2009 09:22:02 GMT

Does AD have a VDSP tool version that can be used for development with ALL DSP Processors from Analog Devices. ( atleast Balckfin and Tigersharc).

If yes can some one give me a link to the page where I can generate its part number.

Further does the ADZS-USB-ICE support all DSP processors.

SigmaDSP ICs supporting selfboot

analog@sgaur.hosted.jivesoftware.com — Thu, 03 Sep 2009 13:42:48 GMT

Which SigmaDSP parts support selfbooting from an EEPROM?

Power consumption increses after new project creation

analog@sgaur.hosted.jivesoftware.com — Tue, 13 Oct 2009 15:38:30 GMT

I was using Visual DSP++ for last 1 month on my product containing ADSP-BF537 processor.
The current consumption it was showing was 320mA.
Taday i created a new project and connected the JTAG.
The current consumption is increasing to 580mA and the processor is getting heated.

Can you please help us.
Its very urgent

Installing U-Boot on BF561 EZKit using VDSP++ flash programmer

analog@sgaur.hosted.jivesoftware.com — Fri, 11 Sep 2009 17:54:57 GMT

the u-boot files from blackfin.uclinux.org I dowloaded are only in *.bin, *.ldr, or *.elf format

from archive "u-boot-bf561-ezkit-2009R1-rc3.tar.bz2":

u-boot-bf561-ezkit-para-2009R1-rc3.ldr

u-boot-bf561-ezkit-init-2009R1-rc3.elf

u-boot-bf561-ezkit-bypass-2009R1-rc3.bin

u-boot-bf561-ezkit-2009R1-rc3.elf

Within VDSP++ I have loaded my flash driver and I'm ready to program the flash w/ u-boot. However the wikis for this do not go into detail for using VDSP++, and they mention that the u-boot file should be converted to a filename.hex.ldr format.

How is this conversion done? I know VDSP++ can handle .bin files but I don't think the u-boot-bf561-ezkit-bypass-2009R1-rc3.bin file will get me where I want to go (being able to boot u-boot from on-board flash).

Has anyone done this before using VDSP++?

I intend to develop using linux after getting u-boot running over my ezkit's serial comm port, but until then the forums at blackfin.uclinux.org generally aren't helpful for VDSP++ related questions.

Any help is greatly appreciated.

How can I get drivers for Analog Devices codecs that are used in my PC sound card?

analog@sgaur.hosted.jivesoftware.com — Mon, 26 Jan 2009 15:50:58 GMT

How can I get drivers for Analog Devices codecs that are used in my PC sound card?

Out of memory in output section 'seg_dmda'...

analog@sgaur.hosted.jivesoftware.com — Wed, 07 Oct 2009 10:20:41 GMT

hallo....

[Error li1040] "C:\Programme\Analog Devices\VisualDSP 5.0\213xx/ldf/ADSP-21369.LDF":256 Out of memory in output section 'seg_dmda' in processor 'p0'
Total of 0x4283 word(s) were not mapped.

how to increase this section or use other memory for linking....

I haven't much expierence about that....

thanks....

Developing Sigma DSP Cluster

analog@sgaur.hosted.jivesoftware.com — Wed, 29 Jul 2009 14:46:51 GMT

This thread has been moved from this category to the new SigmaDSP Processors category. You may find ongoing discussion concerning this subject here: Developing Sigma DSP Cluster.

Thank you, ADI DSP Forum Admin.

LCD Driver and Audio Driver combined. BF548

analog@sgaur.hosted.jivesoftware.com — Tue, 27 Oct 2009 22:26:14 GMT

Hi,

I was told to make a thread to dedicate to this discussion.

I have made a program to recognise words, by modifying the audio loopback program. Currently the detected word is being displayed on the console window.

This is slightly raw, and I would like to make it display on the LCD of the BF548. I've tried compiling the lcd driver with the program (the driver only displays bmps which you specify), but to no avail.

What I'm requesting is a modified LCD driver, which can simply display what's on the console, into the LCD display, or even te command for the LCD driver to display text.

ie: Word detected: At the moment, we're simply printf("word detected is ... etc

What we would like to do, is: printf to the LCD, or simply display everything on the console to the LCD. We don't want to bring up bitmaps, as this would require extra time to access the HDD. We'd prefer the simplest, fastest display possible.

Could you guys help me out with this?

Thanks.

Where do I go from here?

analog@sgaur.hosted.jivesoftware.com — Sat, 05 Sep 2009 18:04:29 GMT

I want to break in to the field of DSP development. When I studied for my BS at Cal my focus was signals and systems. I did take the Discrete Time Signal Processing course, the only one offered at the undergrad level for DSP. But, since I graduated in Dec of 2003 I have not been able to find employment doing DSP design. I have designed embedded systems in C and Assembly. However, I was laid off June 30 and cannot find work.

My question is what tools should I get experience with in order to obtain employment? I'd like to do Pro Audio, designing effects and/or compression algorithms. I cannot get any answers from the businesses to which I've applied. The job descritptions typically require 5 yrs DSP development experience.

I'm really frustrated! Should I go back for a Master's in EE? Should I spend a small fortune on development tools? I'd like to do development work with Sharc processors. Do I need to use Matlab?

How does one break in to this field?

Thanks for any advice,

Greg

Where can I send my questions I don't want to post in this forum?

analog@sgaur.hosted.jivesoftware.com — Tue, 04 Aug 2009 13:56:42 GMT

I have some SigmaDSP and SigmaStudio questions that I don't want to post in a public forum like this one. Where can I send those questions to be answered by a SigmaDSP applications engineer?

BF EZ-LITE kit and VISUAL DSP

analog@sgaur.hosted.jivesoftware.com — Thu, 01 Oct 2009 09:16:21 GMT

Hi,

I do consider of buying an EZ-KLITE starter kit for developing a realtime compression algorithm on Blackfin.

However I am skeptical about the VisualDSP evaluation. Is there any limitation on the VisualDSP's version

included on the kit (example a 90 days trial....program size limitation etc...) or not?

Compressor

analog@sgaur.hosted.jivesoftware.com — Thu, 23 Jul 2009 23:43:40 GMT

I am using sharc 21369 in my project. I was wondering if anyone can provide me a compression algorithm or point me to some documentation on implementing the compressor.

Thanks

RAZ

HDMI EZ LITE Kit

analog@sgaur.hosted.jivesoftware.com — Sat, 08 Aug 2009 18:32:17 GMT

Hi,

I purchased ADZS-BF561-MMSKIT from a distributor, but this only works on NTSC/PAL signals. I

was wondering if there is something equivalent for HDMI signals. My primary concern is that there

are a video in and video out ports, room for software, fast ADSP processor (ex. BF561), and helpful

software tools.

Is there something out there like this? If not AD, maybe another vendor?

Thanks!

SigmaDSP Export Parameters

analog@sgaur.hosted.jivesoftware.com — Wed, 21 Oct 2009 16:57:36 GMT

Hello,

I'm using an ADAU1761 and I?d like to transfer the project builded with sigmastudio in a microcontroller in order to program and manage the codec by fw.

I saw that making a "Export Sytem Files" some include files are generated.

I didn't find the "SigmaStudioFW.h" include file called from one of .h generated by sigmastudio....

Do you have an idea where to find this file?

Do you have an example how to initialize the codec by I2C using these files?

Regards

Stefano

What is the best evaluation board for a SigmaDSP novice?

analog@sgaur.hosted.jivesoftware.com — Tue, 28 Jul 2009 18:15:45 GMT

I am new to the SigmaDSP product line.

What is the best evaluation board for a SigmaDSP novice?

SPI on ADSP21371

analog@sgaur.hosted.jivesoftware.com — Mon, 02 Nov 2009 20:57:29 GMT

I saw that in booting via SPI - the SPI signals of the primery SPI port are by default on the DPI pins 1 to 4. Do i have to connect the signal to these pins again via SRU1 and reconfigure them for output or input?And at this time the SPI is in slave mode.

And i want also to connect the ADSP21371 to Audio codec ADAU1361 and to use the second SPIB in master mode and SPORTS. Using the SPORTs 0 & 1 they uses one clock , frame signals of the codec. So is it necessarily to connet the clock and frame signals twice on the DAI pins - clock and frame signal of SPORT0 and again clock and frame signal od Sport1 on other pins. Or can i connect only the signals of one SPORT an the Data signal of the secon Sport withought the frame and clock signal of the second Sport?

Problem with Chained DMA via External port and IIEP register

analog@sgaur.hosted.jivesoftware.com — Thu, 15 Oct 2009 12:50:00 GMT

Hello,

I am experiencing some problems with chained DMA. I'm DMAing from SDRAM to internal via the external port. I am using a SHARC 21369 in a mixed C and ASM project. The portions pertaining to the DMA are written in ASM. I am trying to to create a 4-part chained DMA. I feel as though I have set up my TCBs and initiated the transfer correctly. They are attached in the included text file.

After I run the DMA, I break at the completed interupt and check the External Port DMA Addressing registers for correctness. Everything looks correct and in order except for one bit. I see that both the Internal and external address have incremented by count and modify properly. That is with one small exception. The final value for the IIEP register should be BA72E. Instead it is 3A72E. This is a difference in the 19th bit. Is there any restrictions on the width or value of the IIEP register? The intended address points to a valid buffer in Data memory. I don't see what the problem here could be. Any ideas?

Thanks in advance,

Glen

@@Hexadecimal
1st TCB
[000B8188] 0x000B8193
[000B8189] 0x00000001
[000B818A] 0x00200000
[000B818B] 0x0000009C
[000B818C] 0x00000001
[000B818D] 0x000BA4BE
2nd TCB
[000B818E] 0x000B8199
[000B818F] 0x00000001
[000B8190] 0x00A00000
[000B8191] 0x0000009C
[000B8192] 0x00000001
[000B8193] 0x000BA55A
3rd TCB
[000B8194] 0x000B819F
[000B8195] 0x00000001
[000B8196] 0x08000000
[000B8197] 0x0000009C
[000B8198] 0x00000001
[000B8199] 0x000BA5F6
4th TCB
[000B819A] 0x00000000
[000B819B] 0x00000001
[000B819C] 0x08800000
[000B819D] 0x0000009C
[000B819E] 0x00000001
[000B819F] 0x000BA692

Logic behind exception handler anomaly code on Blackfin BF533 V0.5

analog@sgaur.hosted.jivesoftware.com — Sat, 10 Oct 2009 19:30:11 GMT

Given that CC = R7 == R7 should always be true

What is logic behind the test and jump in the following anomaly code on silicion 0.5 on BF533

EX_EXCEPTION_HANDLER(InstructionWatchException_TestInsertion) {
[FFA0FDF8] [ -- SP ] = ASTAT ;
[FFA0FDFA] CC = R7 == R7 ;        ******** ALWAYS TRUE
[FFA0FDFC] [ -- SP ] = P0 ;
[FFA0FDFE] P0 = 20 ;
[FFA0FE00] P0.H = 0xffc0 ;
[FFA0FE04] IF CC JUMP 4 /*0xFFA0FE08*/ ;    ******** ALWAYS JUMP
[FFA0FE06] R7 = [ P0 + 0x0 ] ;               ********** WHAT SHOUL:D HAVE BEEN IN R7 that needed to be changed?
[FFA0FE08] P0 = [ SP ++ ] ;
[FFA0FE0A] ASTAT = [ SP ++ ] ;
[FFA0FE0C] LINK 0x0 ;
[FFA0FE10] [ -- SP ] = R0 ;
[FFA0FE12] [ -- SP ] = P1 ;

Use AdvanceExpertDAI to set up DAI pins as GPIO (outputs) for 21368 ?

analog@sgaur.hosted.jivesoftware.com — Mon, 21 Sep 2009 15:36:58 GMT

Hi,

I am trying to use 6 DAI pins as 6 outputs to control some leds. Could you please tell me more details about how to use the latest version of AdvanceExpertDAI for those configuration on 21368?

I thought , for example, choose MISCA0~ MISCCA5 as source singals and any of DAI_PINx as the Destination?

But the AdvanceExpertDAI doesn't show any of MISCAx as a source, then how to set up those GPIOs I need?

Thanks for any suggestion!

Tao

How can I implement a Linkwitz-Riley filter?

analog@sgaur.hosted.jivesoftware.com — Wed, 12 Aug 2009 18:46:52 GMT

I want to use a 4th-order Linkwitz-Riley filter as a crossover in my system, but I don't see it available in the SigmaStudio library. How can I build this?

1940 includes reverb but 1701 and others dont ?

randyperkins@randyperkins.com — Wed, 30 Sep 2009 04:49:36 GMT

Hello

I am considering ordering an evaluation board and have been looking over sigma studio.

I noticed the AD1940 includes reverb under ADI algorithims but the ADAU1701 does not.

Is there a list of which feature set is available with each chip ?

thanks

rperkins

SIMD Question

analog@sgaur.hosted.jivesoftware.com — Thu, 15 Oct 2009 10:11:55 GMT

Hello!

I have a some questions concerning single instruction multiple data (SIMD). I heard that I only can use SIMD, if I do the same operations on two channels simultaneous. For example filtering the right and left channels of an audio signal simultaneous. Otherwise I found only library functions for a single channel e.g. FIR-filter, but these functions are already optimized for SIMD.

My questions:

Is it generally better to process (filter) multiple channels simultaneous or sequential. Can I use SIMD, if I call 2 library functions which do not use SIMD (e.g. fir_interp).

Best regards

Thomas

Multichannel Receive SPORT DMA issue

analog@sgaur.hosted.jivesoftware.com — Fri, 02 Oct 2009 15:28:27 GMT

I am trying to interface BF527 SPORT to receive multichannel data (8 16bit channels) from an external source (DDC). I want to use the DMA to buffer a number of data samples before interrupting the CPU using ping pong buffereing scheme between DMA and CPU. I have been digging through but can't find an example that does something similar. I have the attached code that works for the most part, data gets through SPORT and DMA fills the buffers but the DMA call back never returns and remains in an infinite nesting ISR loop. The result is that the CPU (whil (1) loop) never gets to run (processBufferCount stuck at 1 and processErrorCount keeps incrementing). Can someone help me find an example or take a look at the code and comment what could be wrong here? Thanks

[Interrupt Manager] Unhandled Interrupt?

analog@sgaur.hosted.jivesoftware.com — Fri, 25 Sep 2009 00:46:13 GMT

Howdy,

I'm working on a Blackfin (536) based system that runs lwIP and VDK, and thus the Interrupt Manager.

lwIP registers a handler for the MAC Error interrupt; the same pin also handles CAN, PPI, SPORT, UART, and SPI errors. I register a secondary handler for UART errors. I am currently getting instances in which my handler is called (presumably after lwIP failed to handle the interrupt), but there are no errors on either UART0 or UART1, which makes me think that I may be getting errors from some other (unused) peripheral. (I'm not using the CAN, PPI, or SPORT, and the only possible SPI error condition should never happen and should force the SPI into slave mode if it does, which isn't happening.)

Anyway, my handler scratches its head and then returns ADI_INT_RESULT_NOT_PROCESSED. What happens if all the handlers registered on a particular interrupt return 'not processed'? Stepping seems to indicate that the system looks for further handlers, fails to find them, and then just goes on as if it was handled?

If there is no handler registered for an interrupt at all, will you get an exception of some sort if that interrupt occurs?

Challenge round: The interrupt in question appears to be causing a line of my code to fail to be executed, which I would have said was impossible. In particular, I'm initializing UART1. If I run to the line in which I clear DLAB (having set up the baud rate) and step over it: 1) I get the interrupt, and 2) the line executes, clearing DLAB and clearing me for further operation. If, on the other hand, I run to the _next_ line of code the DLAB bit is not cleared and the UART sits there waiting for further baud rate updates. If I protect the UART init function with an unscheduled region, it functions smoothly, but I shouldn't need to protect it, as there are no other threads that use UART1 or its registers. Any ideas?

Thanks,

Alex

ADSP-2137x connect through the Summit-ICE Emulator

afinko@gmail.com — Mon, 26 Oct 2009 13:58:25 GMT

I have the Summit-ICE Emulator that I was using with the ADSP-2181 few years ago.

It is possible to emulate the ADSP-21371 in Visual DSP++ through this emulator?

Thanks,

Afinko

Compiler error?

analog@sgaur.hosted.jivesoftware.com — Tue, 20 Oct 2009 07:13:15 GMT

Hi !

I use a structure which is stored in ext.SDRAM and my function code is also in ext. prgmemory.

but my code fragment which is an if declaration which use a var contained in this structure seems to be missinterpreted if i look at the generated asm code (see my screenshoot of my VDSP)

my structure(shown below) : if i use bigger(u32) vars before the smaller vars - look at marked line - the access to the next following members seems to be wrong. i have never observed this behaviour. So i move u32 declare after the u8 vars and it works but i guess that the compiler have to handle this.

i know that memory is saved if i declare smaller vars before bigger ones.(allignment etc).

typedef struct stationSettings { //macAddress[6]; // char[6];   //6bytes for a macaddr
volatile bool onAir;   //true if connected via lan
   bool running;     // set after main loop is reached
   bool LANReady; //if lan device driver is opened->link established
   bool firstTimeAfterLinkUP;   //true after linkUp used to send the JoinIntoCommand
   bool stateChange; //flag to sign a statechange since last check
   bool sendCyclicData;
   bool DSPUartActive;
   bool isPitB107;      //specialFlag to identify PitBuilding107
   bool isAddP122;      //specialFlag to identify AddPitBuilding122
   bool isPlayer102;    //specialFlag to identify player STID=102
   bool PitB107Active;
   bool AddPB122Active;
   bool SDCardPluggedIn;
   u32 stateChange_content;
   u8   VLAN_PCP;    //priority used for VLAN audio
   u8   audioSystem[2];
   u8   FWVersion;
   u8   HWDetect;
   u8   HWOptions;
   u8   SMM_Priority; //priority for SyncMasterModule changes-joins..
   u8   faultStateCOP; //used for several faultStates

   u8   extUARTProtocol;
   u8   extUARTMode; // new 24.08.09 -- since protov0.8 FW Build4
   u8   SoftwareID;
   u8   SPriority;
   u16 SysLogInterval;
   u16 cyclicDataInterval;
   u16 reqStationCount;

   u16 stationID;   //12bit are effectifely used to mark a station with an ID
   u16 VLAN_ID; //used to sep. store from packetized VLAN_Station_ID
   u32 extFaultStateCOP; //int used additional info

} STATION_SETTINGS;

BF518 EZ Board - Orcad files

analog@sgaur.hosted.jivesoftware.com — Wed, 05 Aug 2009 13:54:41 GMT

Hi All,

Do we provide the Orcad files for BF518F EZ board ? If yes, where can I find it ?

Best regards,

Hubert

Warning: External memory is disabled for this region of memory

analog@sgaur.hosted.jivesoftware.com — Fri, 05 Jun 2009 11:59:22 GMT

Why do I encounter the message 'Warning: External memory is disabled for this region of memory' when I start VisualDSP++?

How do I use the GPIO / MP pins on the SigmaDSP?

analog@sgaur.hosted.jivesoftware.com — Tue, 28 Jul 2009 16:32:39 GMT

I am using a SigmaDSP with GPIO (General purpose input/output) or MP (multi-purpose) pins. How do I make use of them in a system design?

BF518 drive strength control

analog@sgaur.hosted.jivesoftware.com — Wed, 21 Oct 2009 02:47:16 GMT

For each pin of the processor BF518 different IBIS models depending on a driver strength are given.

As it is possible to control a driver strength?

GP Timer on DAI? 21368

analog@sgaur.hosted.jivesoftware.com — Thu, 01 Oct 2009 19:44:35 GMT

According to the Programmers Reference, the GP Timers can be connected to a DAI pin as an output. This is contrary to the SRU listings and the hardware block diagram. I have a situation where I have too much activity on the DPI and very little on the DAI port, so I'm forced to choose which goes where.

Thanks.

ADV7184 Video Decoder Schematic

analog@sgaur.hosted.jivesoftware.com — Thu, 08 Oct 2009 16:13:35 GMT

Hello,

I have a question about the 'typical circuit connection' on page 111 of the ADV7184 data sheet.

Many thanks,

Owen

ADAV801 in Audio Extender

analog@sgaur.hosted.jivesoftware.com — Fri, 23 Oct 2009 13:03:53 GMT

Hi, We are using BF-533 Ez-kit Lite along Audio extender card for our application. System Usage: Ø We are giving digital input and playing back using analog o/p. Ø The digital i/p is received using ADAV801 and played back using AD1938. Ø The sysclk3 of ADAV801 is given as mclk for AD1938. Ø The configuration of ADAV801 is attached. The format of configuration is ( regaddress<<1: data) Ø PLL Control Register is configured as SYSCLK3 is the recovered S/PDIF clock from DIRIN and 512*fs as output for SYSCLK3. Issue: When we are giving a sweep signal [200Hz to 20KHz] as input, the output is terminated at around 13Khz. Observation: With our configuration, SYSCLK3 is coming as 12.288 MHz, but it supposed to come as 24.576 MHz. Can you please check our configuration registers and lets us know whether we are making any mistake? This is very urgent for our system development. With regards, Sunil

Use of Linker Overlays for Blackfin ?

analog@sgaur.hosted.jivesoftware.com — Thu, 29 Oct 2009 17:14:12 GMT

Hello-

I'm looking for any pointers regarding the use of Linker Overlays for the Blackfin.

I'm currently using the JPEG decoder, and want to be able to use the MP4 decoder but lack sufficient on-chip memory (BF-531). Since I don't have to use both of these IP modules at the same time I would like to be able to overlay them for their on-chip resource usage. I don't know if this is possible to do with software object modules (libraries) that I don't have the source for.

Have seen the EE-66 and EE-67 appnotes and the VDSP 5 Linker Manual.

Thank you,

Steven J. Ackerman, Consultant

ACS, Sarasota, FL

http://www.acscontrol.com

Where can I find a description of the changes made in the latest SigmaStudio revision?

analog@sgaur.hosted.jivesoftware.com — Tue, 28 Jul 2009 16:42:05 GMT

Where can I find a description of the changes made in the latest SigmaStudio revision?

Project Building Error - An invalid argument was encountered

analog@sgaur.hosted.jivesoftware.com — Fri, 16 Jan 2009 20:38:55 GMT

When building a project I encounter a dialog box with the following error: "An invalid argument was encountered". What's the cause of this error and how can I avoid it?

Maximum clock freq for adsp21363 Jtag TCK input

analog@sgaur.hosted.jivesoftware.com — Wed, 07 Oct 2009 18:15:46 GMT

We have a HPUSB-ICE that we use with the ADSP21363. It allows JTAG clock frequencies from 10-50MHz.

One of our products uses a 12Mhz oscillator for the CLKIN input and core-clock is set to 192Mhz, the other product uses a 24MHz oscillator and the pll is set to generate a 324Mhz core clock.

We've been happliy running the HPUSB-ICE with the 50MHz clock for many years. Today I noticed the spec that states the minimum period on the TCK input is the period of the CLKIN pin, and not some small multiple of the core-clock period.

Did I interpret it correctly? With a 12Mhz oscillator I should run the HPUSB-ICE at 10 MHz, and even with a 24MHz oscillator, I can't run higher than 20 Mhz?

Bob Kruse

Engineering Samples vs X-grade and production released products?

analog@sgaur.hosted.jivesoftware.com — Fri, 03 Apr 2009 17:51:57 GMT

What is the difference between Engineering Samples, X-grade and production released products?

Report on exception behaviour under VDSP Update 5.7 simulator

analog@sgaur.hosted.jivesoftware.com — Mon, 09 Nov 2009 03:59:59 GMT

Am looking at watch point operations a with BF533

Under Update 5.5 -- simulator

Gets in exception "once" for instruction watch match

Ignores data watch operations

We discussed issues about what to expect with the new update -- i.e. not to expect everything to be fixed in 5.7.

However have come up with a couple of unexpected issues with update 7

Under Update 5.7 simulator

instruction watch match

You said that simulator would work with 2 instruction watch point registers using a range, but not with 1 instruction watch point watching a single location

Actually I find that I get into instruction watch exception -- "every other instruction access" when using a single register for watching

This might suggest that the simulator control register for watch point

Gets into exception -- "every other time" for instruction watch match

Given the fact that I am only using 1 instruction watch register and not a range -- does this suggest an issue with the way the control bits are being handled (or just the fact the simulator defaults to watching a range regardless of setting).

AM surprized that it works "every other time"

As you indicated simulator to handle data watch match in later issue

Am going to try and configure settings to work with a range of instructions (of size 1) and see what I get

Boot Flash? VDSP 5.0 and 21368

analog@sgaur.hosted.jivesoftware.com — Thu, 01 Oct 2009 13:31:31 GMT

Hello;

I have my code stable enough that I would like to try running free-standing. So I invoked the Flash Programmer and browsed to the 369_prom.dxe file and clicked "Load Driver" which gave me the following message:

Error: Failed loading driver
C:\Program Files\Analog Devices\VisualDSP 5.0\213xx\ldr\369_prom.dxe
Please verify that the file is compatible with the
ADSP-21368 target and that the path is valid.

So I tried the other likely file:

Error: Failed loading driver
C:\Program Files\Analog Devices\VisualDSP 5.0\213xx\ldr\36x_prom.dxe
Please verify that the file is compatible with the
ADSP-21368 target and that the path is valid.

That's discouraging...

Please advise.

Thanks.

Causing message on VDSP screen and then pausing

analog@sgaur.hosted.jivesoftware.com — Sat, 26 Sep 2009 15:31:09 GMT

I thought the following would put out a message and cause VDSP to pause till the gets was completed

-- but it does not. I would prefer not to have to use break points

I used to pop up some sort of response window in VDSP -- just can't remember syntax -- any body help. Not sure what to look for under "help"

#include <stdio.h>

void GetBuffer(char *buff) {

puts("If gets( ) is not waiting -- then set a break point at this line of code\n");
puts("Waiting for you to hold the switches down and then press return");

gets(buff);
}

Thanks

Which VisualDSP+ products support BTC (Background Telemetry Channel)?

analog@sgaur.hosted.jivesoftware.com — Thu, 12 Feb 2009 12:52:36 GMT

Which VisualDSP+ products support BTC (Background Telemetry Channel)?

SPI slave core transmit problem

analog@sgaur.hosted.jivesoftware.com — Mon, 03 Aug 2009 11:50:15 GMT

Hi,

I'm trying to set up a SPI link between two Blackfin processors.

The master Blackfin is using DMA for receive and transmit, the slave device will use core mode (TIMOD 01 and 00).

The hardware link between both devices is working, the slave is receiving and transmitting data from/to the master.

But the received and transmitted data is corrupt. It looks like data is shifted by one bit or the last bit is missing. Looking on the signals by an oscilloscope shows that the ISR routine is called at the very beginning of the last bit, before it is sampled (in SPI mode 1 and 3). In SPI mode 0, ISR triggering is OK but data transmit by slave starts one bit later than expected thus the last bit is not transmitted correctly.

on the master SPI_CTL = 0x1c06

on the slave SPI_CTL = 0x4c24

Slave select is handled by software.

Any help on this problem is appreciated.

Best regards

Sebastian

How to integrate user original algorithm to SigmaDSP?

analog@sgaur.hosted.jivesoftware.com — Mon, 31 Aug 2009 07:59:18 GMT

How to do on SigmaStudio, when user want to integrate an original algorithm to SigmaDSP?

VisualDSP++: an annoying behaviour

analog@sgaur.hosted.jivesoftware.com — Mon, 19 Oct 2009 11:50:55 GMT

I've been using VisualDSP++ since the 3.5 version and I've never found a way to avoid an extremely annoying behaviour: if you select to activate an emulator session and the operation can't be successfully performed, or the target request to disconnect during an emulator session, VisualDSP++ looses the session layout (debug windows, register windows, ...).

When you are able to restart this session only the disassembly and the output windows are visible...

All the layout you have previously configured as needed (memory, plot, register, ...) is lost, and you have to recreate it from scratch...

Really time-wasting

How can I avoid this?

Including raw binary file in Vdsp++

analog@sgaur.hosted.jivesoftware.com — Tue, 06 Oct 2009 14:40:20 GMT

Hi all,

I have a raw binary file (.rbf from altera fpga programming file) i am trying to initialize this as a binary data in the project and access this later in the application . is there any way to complish this?

I looked in to the .INC/BINARY but i am unbale to successfully complile this .

can i use this one in a C file? or this has to be in ASM file?

.SECTION constdata;

.INC/BINARY Image1[]="fpgaimage.rbf";

Thank You

Shridhar

low cost emulators

analog@sgaur.hosted.jivesoftware.com — Fri, 23 Oct 2009 06:46:33 GMT

TI has a native double float support and low cost emulators. So it's very attractive.

So far our firm used ADSP-218x (about 1000-2000 piece in year), ADSP-2191 (about 50-100 piece in year). For Russia it's a big purchase amount.

ADSP-21992 (about 25-50 piece in year) processors. Now we want to develop a new high-performance control system. And we saw that AD has a poor support and invalid promotion of processor production that TI:

1. Lack of support of 40-bit float point feature in C/С++ VDSP++.

I udnerstand that it's to support I must to declare 40-bit width of the internal memory and turn off RND32=0. So I get 40-bit float point support. That to use 40-bit float point feature in C/С++ VDSP++ I learn Sharc's manual and search in forums. The application from AD is absent. It's very bad.

Besides that it's a problem of saving in external memory 40-bit float point.

TI has a native support of the double float point.

2. Lack the low cost emulators with BTC for customer's target boards

The low cost emulators with BTC can become the standalone debug agent. It's very good idea to use in the low cost emulators the Blackfin's processors.

TI has low cost emulators which the price is lower than AD's.

Do AD plan to a new sale programm "piggy-back promotion ": VDSP++ and ADZS-HPUSB-ICE ? As it was December 2008 - January 2009?

Visual audio development

analog@sgaur.hosted.jivesoftware.com — Tue, 13 Oct 2009 02:35:24 GMT

Hi ,

I would like to know how to set Bessel / Butterworth/ Linkwitz-Riley filters by using VisualAudio ? Is there someone charge for it ?

Thanks .

regarding time -frequency domain

analog@sgaur.hosted.jivesoftware.com — Fri, 11 Sep 2009 07:14:48 GMT

hello ,

i have a doubt in time frequency conversion ... why a rapidly changing signal require a large bandwidth..

why a very high frequency sine wave it self appears as a impulse at that particular frequency in frequency domain ,since it is rapidly changing with respect to time it should occupy a high band width but instead its representation is only a impulse in frequency domain.

and the other doubt is , consider a sine wave of fixed frequency but varying amplitude as a function of t. for this how the spectrum in frequency domain look like

i consider tha answer to be for the last question as a impulse at that particular frequency whose amplitude varies

Can I turn off power to some logic in my circuit and keep power on other logic?

analog@sgaur.hosted.jivesoftware.com — Tue, 14 Apr 2009 19:41:13 GMT

Can I turn off power to some logic in my circuit and keep power on other logic? Will this save power? When I try it, why do some chips get hot?

audio routing question

analog@sgaur.hosted.jivesoftware.com — Mon, 07 Sep 2009 07:31:43 GMT

Hi,

We are using AD144x DSP and have one 4-channel TDM input. All four channels are in 48kHz and 16-bit, very straight-forward. The only issue with this is the TDM slot ordering of different audio streams can be varying. For example, in one frame the ordering is ch1, ch2, ch3, ch4, and the next could be ch4, ch1, ch2, ch3. To route the input streams to the proper output channels, I'm thinking to use 24-bit data, with the most significant byte containing the channel id, i.e. 0x01-0x3 concatenated with 16bit audio data. On the DSP side, I'm thinking to have a comparator (or more) to route the channels and shift the input data left by 8 bits to get the real audio data, then feed it to the processing blocks. But I just can't see how it can be done in SigmaStudio. What blocks can I use for this kind of purpose? Is it doable or there's some other alternative? Thanks.

Regards,

Rong

Is changing clock frequency on Blackfin glitchless

analog@sgaur.hosted.jivesoftware.com — Tue, 20 Jan 2009 18:49:08 GMT

Is the coarse frequency adjustment glitchless?

"Target halted at breakpoints "

analog@sgaur.hosted.jivesoftware.com — Thu, 17 Sep 2009 14:59:38 GMT

Hello,
My board is ADSP-BF518F Evaluation Board, and with VDSP++ 5.0
Today I changed one line in my c program, then built the project as usual.
But this time, a dialog window came out saing "Target halted at breakpoints".
At the same time, the debug information is shown as:

Target halted due to software breakpoint but no breakpoint found at address: 0xXXXX
Possible reasons are:
1.An embedded breakpoint (EMUEXCPT instruction) in the code
2.A breakpoint is placed at the last instruction of a do() loop

After that, I ran the program and stop it in VDSP, the dialog came out again,
while the program can never go forward from then on. What's wrong with it?

Really thanks!

How to get an announcement of SigmaStudio Version Up?

analog@sgaur.hosted.jivesoftware.com — Tue, 08 Sep 2009 02:25:36 GMT

Hello!!

I want to get an announcement of SigmaStudio (SS) Version Up via mail?

And how to share the old version SS with latest version?

Ryosuke

BF527 Power Managment

analog@sgaur.hosted.jivesoftware.com — Fri, 16 Oct 2009 00:18:45 GMT

Using a BF527 I'm trying to reduce power. Can't use Sleep mode because Ethernet connection stops. Have reduce SCLK speed and that saves some power but using the PLL_CTL doesn't seem to work. Any suggestions

very fast CRC32 code wanted

analog@sgaur.hosted.jivesoftware.com — Tue, 23 Jun 2009 13:47:40 GMT

is there any highly optimized crc32 algorithm for BF537?

i need a very fast implementation

regards chris

Doubts about the assembly of the AN-679 (A Low Cost Watt-Hour Energy Meter Based on the ADE7757 (AD71056)) in Brazil.

analog@sgaur.hosted.jivesoftware.com — Sun, 21 Jun 2009 22:59:00 GMT

Hello

friends from Analog Devices!

I am a university student from Brazil, and I am designing a measurement system and power management based on application note AN679.

Well, did the assembly of a PCB according to reports AN679, but I'm having questions in which I report below.

* Doubts/ problems:

1) application AN679 is designed for 220v or 127 volts?
because according to Figure 1 of the AN679, we see that the PCB is connected to a phase line and a neutral line, so I suggest this configuration is 127 volts, since here in Brazil, the lines that reach the user are :
1 phase + 1 neutral = 127 volts (60Hz)

1 phase + 1 phase = 220 volts (60Hz)

I need help on this.

2) I produced a PCB according to the specification AN679, but noticed that when connecting to a line 127 volts or even 220 volts,

can not have 5 volts at the entrance of the Vdd of the AD71056.

As I disconnect the power supply side of the power of the ADI side, in other words when I remove the pin from voltage regulator LM78L05 output, oh yes !!!!!

I get 5 volts at the output of voltage regulator. but if I connect again the power of ADI, I again can not have 5 volts at the entrance of the Vdd of the AD71056.

what may be causing this error?

Please see the attached files

How can I change parameters on-the-fly in an application without SigmaStudio?

analog@sgaur.hosted.jivesoftware.com — Tue, 28 Jul 2009 18:08:27 GMT

My target system will have a microcontroller which i will use to control the signal processing parameters in real-time.

How do I calculate the values of the parameters I want to update?

SPORT WITH EXTERNAL CLOCK & FS > "ADSP-21262"

analog@sgaur.hosted.jivesoftware.com — Thu, 22 Oct 2009 07:55:52 GMT

hello,

I need to use the SPORT in multichannel mode (SPORT0 in TX and SPORT1 in RX) with external CLOCK & FS. I can not find any example. I tried to configure the SPORT in this mode, without any results. Can I have some help or examples?

thank you

Lockbox - compliance to standards

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Apr 2009 10:06:34 GMT

Do the BF52x and BF54x processors comply with EAL 3+, 4 standards? If not, what standards do they comply with?

Image Proc. Toolbox

analog@sgaur.hosted.jivesoftware.com — Thu, 22 Oct 2009 08:07:13 GMT

This thread would be better placed in the Software Modules, Starter Kits and Software Development Kits Tools category, and has been moved here:Image Proc. Toolbox

Thank you.

Core Hang

analog@sgaur.hosted.jivesoftware.com — Mon, 02 Nov 2009 15:45:39 GMT

Hi,

when I want to halt my programm following error occours:

"Core Hang Detected on Device 0"

For a more detailed description please look at the screenshot below.

I'm not sure at the moment which information are necessary for you to solve the problem. Please let me know.

Best regards,

Marc

Diode connected between the VDDint and VDDext rails

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Apr 2009 09:38:36 GMT

What is the purpose of the D7 diode between VDDint and VDDext rails on the BF561 EZ-KIT Lite?

attempt to use SWRST by a TS201 to reboot itself

analog@sgaur.hosted.jivesoftware.com — Sun, 26 Jul 2009 08:20:04 GMT

I'm working with the TS201 tigersharc using a toppology where 3 processors (P0, P1 & P2) are

connected to shared cluster bus. In this topology P0 is the master processor.

My aim is that P0 will be able to reset the whole DSP group (that is to reset P1 and P2 and after that

to reset itself) when desired. After such reset the 3 DSPs are supposed to re-boot from flash and run

again from start.

The code I wrote for this resides in P0 and simply sets the SWRST bit in the EMUCTL of P1 & P2 and later on

sets the SWRST in P0 (that is P0 sets its SWRST bit within its own EMUCTL).

What I see is that P1 & P2 reboot as expected but P0 does not seem to receive sofware reset at all.

Before I issue the SWRST in P0 I changed the NMOD in SQCTL to supervisor mode but this also did not yield the expected s/w reset.

Is there any problem for a tigersharc to reset itself using the SWRST bit in its own EMUCTL?

If not, what should I do in order to make P0 reset itself this way?

I'll appreciate any insights?

Thanks you.

Sharon

VDK and idle state

analog@sgaur.hosted.jivesoftware.com — Thu, 30 Jul 2009 12:35:12 GMT

Hi,

I use VDK in my application with blackfin processor 537.

I was thinking of putting the core in idle state that may save some power, when there is not much to do for DSP. I tried this with simple code as follows.

#CLI R0 ;

#IDLE ;

#STI R0 ;

And failed. With crash!

I could not think of a best place to do this other than VDK idle thread. Taking care that 'wakeup' is enabled for all the concerned peropherals.

Has anybody tried it already ?

dspgeek

SImulator

analog@sgaur.hosted.jivesoftware.com — Sat, 10 Oct 2009 19:45:09 GMT

Trouble was -- I could get the instruction watch exceptions to activate in real life but not on the simulator.

Do either of the Blackfin simulators support the instruction watch or data watch operations?

I presume not -- I will trigger the exception routines a adifferent way and use the pipeline viewer then, but would be nice not to have to.

Thanks

Flash Selection Criteria

analog@sgaur.hosted.jivesoftware.com — Fri, 20 Nov 2009 13:44:19 GMT

Hi All,

I am working on designing a custom baord consisting of Stratix-II FPGA and TigerSHARC ADSP_TS201S.
I am using an auxiliary FPGA Cyclone-II with DSP processor to interface with peripherals.

I require a 128Mb flash to be connected to TigerSHARC processor. Is there any particular selection criteria for FLASH selection, as there is for SDRAM selection? Or should I compare the timing diagrams and properties of FLASH on evaluation board (512k X 8) with other Flash devices?

Presently I am planning to use Numonyx FLASH (16M X 8) JS28F128J3D.

Please reply at the earliest!

Thanks and Regards,

Sid

FFT on SigmaDSP Processor?

afinko@gmail.com — Wed, 21 Oct 2009 08:11:30 GMT

In most materials about SigmaStudio is written that in can handle:

"FIR and IIR filters, dynamics processors, mixers, low level DSP functions, and third-party algorithms for fast development of custom signal flows".

It is possible to compute FFT on any of available SigmaDSP Processor?

Suppressing Build Warnings

analog@sgaur.hosted.jivesoftware.com — Thu, 29 Oct 2009 00:52:34 GMT

Hello,

We use ADI AES assembly files, (aes_init.asm, aes_cipher.asm, aes_key_expansion.asm), in 2 of our VDSP projects. Building with these files we get warnings of the form:

[Informational ea1056] "..\..\..\src\aes_init.asm":61 Preg read after write which requires 3 extra cycles. We know these are harmless and just want to eliminate them from the build.

In our LoaderDecrypter project we eliminated the warnings by building the files using File Specific Settings and setting the Assemble switch:

-Wno-info. This works fine in this project.

However in the Warrior project which is multi-threaded using VDK we have a problem. When we do the same thing here we get build errors:

[Error li1021] The following symbols referenced in processor 'p0' could not be resolved:

'AESInvCipher [_AESInvCipher]' referenced from '.\DevBoard\valDecDistrImage.doj'

Linker finished with 1 error

cc3089: fatal error: Link failed

Tool failed with exit/exception code: 1.

Build was unsuccessful.

We get the same message for each of the files for which we build using File Specific Settings and set the –Wno-info assemble switch. Any thoughts on how to fix this?

Thanks in advance,

Rob Hutchinson

Visual DSP Struct error

analog@sgaur.hosted.jivesoftware.com — Wed, 26 Aug 2009 05:43:58 GMT

Hi,

I've been writing code, and I've found that basic struct code gets errors.

Here is my code:

typedef struct{
float A;
float U[6];
}model_s;

model_s mm_one;

mmone.A = 0.2;

And here are the errors I get:

".\model_header.h", line 12: cc0077: {D} error: this declaration has no
storage class or type specifier
mm_one.A = 0.2;
^

".\model_header.h", line 12: cc0147: error: declaration is incompatible with
"model_s mm_one" (declared at line 10)
mm_one.A = 0.2;
^

".\model_header.h", line 12: cc0065: error: expected a ";"
mm_one.A = 0.2;
^

3 errors detected in the compilation of ".\process_data.c".
cc3089: fatal error: Compilation failed
Tool failed with exit/exception code: 1.
Build was unsuccessful.

It seems like the compiler is not recognising that mm_one is of model_s type.

How can I get it to work? I've searched everywhere for struct and typedef struct syntax, and I'm quite sure I'm using the right syntax, so what else could I be doing wrong?

Thanks.

TigerSHARC silicon version informaiton

analog@sgaur.hosted.jivesoftware.com — Fri, 10 Jul 2009 06:00:19 GMT

Hi , does anyone know how to get the silicon version from the following information, shoud I think this silicon version is 2.0? thanks!

ADSP-TS201S
ABP2060
1445027.1-R-2.0
#0821 CANRDR
210FV

218x and IRQ1 interrupt not working

analog@sgaur.hosted.jivesoftware.com — Wed, 24 Jun 2009 21:20:42 GMT

Hello,

I'm using the interrupt handler to setup IRQ1 interrupt as well as a timer interrupt

interrupt (SIGTIMER, timer_isr) seems to work fine but interrupt(SIGIRQ1, irq1_isr) crashes the application sent it to __exit, ___lib_prog_term, __Exit in the Disassembly everytime the interrupt occurs.

The IMASK is getting setup correctly and the ICNTL is set to edge trigger, which also correct.

Software Emulation for MDIO Interface

analog@sgaur.hosted.jivesoftware.com — Thu, 12 Nov 2009 15:23:53 GMT

Does anyone have software code to emulate slave side of MDIO (Management Data Input/Output) Interface via GPIO of Blackfin?

http://en.wikipedia.org/wiki/Management_Data_Input/Output

MDIO is known as the interface to connect MAC device and PHY devices for the Ethernet protocol.

However, as another use case of MDIO, there is a CFP MSA Optical Transeiver module. In this application, MDIO is used as an management bus interface between Host and the CFP modules.

Our customer is considering to use Blackfin as the main controller in the CFP module.

In this case, Blackfin is managed by Host via MDIO and should act as slave device.

Some of Blackfin products has MDIO master interface to control PHY devices for the Ethernet, but doesn't have slave interface for this purpose.

So, we are looking for a software emulation code of MDIO slave.

Thanks,

DPI pin used as edge-detect IRQ

analog@sgaur.hosted.jivesoftware.com — Thu, 24 Sep 2009 13:37:46 GMT

I would like to use a DPI pin to trigger an IRQ. I think I'm missing a step. Here's my code.

//Generating Code for connecting : DPI_PIN6 to MISCB4
SRU (LOW, DPI_PBEN06_I);
SRU (DPI_PB06_O, MISCB4_I);

*pDPI_IRPTL_FE |= EXT_MISC_4_INT; // IRQ on Data Ready from DPI6 = MISC4
*pDPI_IRPTL |= EXT_MISC_4_INT; // IRQ on Data Ready from DPI6 = MISC4
interruptf(SIG_DPI, a2dISR);

I have confirmed that DPI_6 sees a falling edge, and I can force a2dISR to run and it works correctly. I have other IRQs that are working (IRQ2, SPI_DMA). As I understand it, I can't use another /IRQ pin as they are level-sensitive, not edge-sensitive.

What am I missing?

Thanks.

Dan

Characteristics of EMUCLK (for benchmarking)

analog@sgaur.hosted.jivesoftware.com — Mon, 21 Sep 2009 20:54:23 GMT

Hi there,

I’m trying to do some profiling of the SPI interface between a 2136x DSP and a host processor (bytes/sec, commands/sec, etc) and am trying to use EMUCLK to limit the ‘recording window' to a certain number of seconds. I just wanted to verify a couple of things:

1) EMUCLK starts at zero and begins incrementing immediately after reset? (It’s active during the boot process, and increments even while idle instructions are executed)

2) It increments at the core-clock rate?

I ask because I’m getting some suspicious results. At the very top of the SPI ISR, where I handle communications with the host, I have this line so that I can subtract the ‘offset’ – i.e. the amount of time that the processor spent booting and setting up, rather than executing normally.

if( gFirstClk == 0) asm("r0=emuclk; dm(_gFirstClk)=r0;"); //update C variable

So, what has me questioning my results is that I’m getting a value of 0x25 for gFirstClk every time? What I do is to power-up the part, and let it run for 10 seconds or so – then I hit connect in the debugger and then halt. (It’s config’d to not do anything upon connection.)

Any ideas?

Thanks,

Matt

How do I install both a floating and node-locked license on the same computer?

analog@sgaur.hosted.jivesoftware.com — Wed, 18 Feb 2009 09:17:13 GMT

How do I install both a floating and node-locked license on the same computer?

Using UART2 or UART3 on the BF548 with system services

analog@sgaur.hosted.jivesoftware.com — Thu, 15 Oct 2009 11:32:12 GMT

Hi,

I'm unable to open UART2 or UART3 using adi_dev_Open() on my BF548. I have stepped through the function, and it seems that there is no DMA channel mapped to UART2 and UART3 RX, which was later confirmed by reading the manual.

The question is: Is there a way to use the system services to operate UART2 or UART3 so the initialization sequence will not fail? Should I map a DMA channel manually?

An example code would be very appreciated.

Thank alot,

Shimon.

kBlockInInvalidRegion - What is the Value Information

analog@sgaur.hosted.jivesoftware.com — Fri, 09 Oct 2009 08:46:38 GMT

Our application sometimes generates the following kernel panic when I call VDK:Sleep.

0x00000001 (panicCode = ThreadError)
0x8000000b (SystemError = kBlockInInvalidRegion)
0x00000006 (value)

I know that kBlockInInvalidRegion indicates Sleep() is being called in an unscheduled region, causing a scheduling conflict (from the VDK user guide).

I have two questions.

1. I would like to know what the value code of 6 indicates. I can not find a description of the "value" argment in the VDK documentation.

2. As well as unscheduled regions created with VDK_PushUnscheduledRegion/VDK_PopUnscheduledRegion is there any other VDK methods that would create an unscheduled region that would cause kBlockInInvalidRegion?

Why is there an ADSP-BF535 processor on my EZ-KIT Lite?

analog@sgaur.hosted.jivesoftware.com — Fri, 16 Jan 2009 20:44:58 GMT

Why does my EZ-KIT Lite include an ADSP-BF535 DSP? I didn't order the BF535 EZ-KIT Lite.

What is the DSP Collaborative?

analog@sgaur.hosted.jivesoftware.com — Mon, 26 Jan 2009 14:52:34 GMT

What is the DSP Collaborative?

SPORT - gate the clock

analog@sgaur.hosted.jivesoftware.com — Mon, 24 Aug 2009 13:58:49 GMT

This thread would be better placed in the SHARC category, and has been moved here: SPORT - gate the clock?

Interfacing Blackfin® EZ-KIT Lite® Boards to CMOS Image Sensors

analog@sgaur.hosted.jivesoftware.com — Fri, 09 Oct 2009 05:36:26 GMT

Hi guys!

There is a link on the Analog website that shows a pdf file about interfacing the Blackfin boards to CMOS image sensors. When I browsed through the pdf file, I was able to read something about a zip file that probably contains the different programming examples for CMOS Sensor interfacing. However, I was not able to find anything about the zip file when I searched for it on the Analog website. Please guys, if there is anyone out there who could direct me to the exact page where I could download the zip file, then please please help me. Your help would be greatly appreciated.

Here is the link that contains the pdf file:

http://www.analog.com/static/imported-files/application_notes/EE_300_Blackfin_Easy_KIT_Lite.pdf

FIR Accelerator

analog@sgaur.hosted.jivesoftware.com — Wed, 29 Jul 2009 14:41:28 GMT

Hello All!

I am using the example code of EE-322 Expert Code Generator to implement a FIR Filter, which works fine. The program generates 4 (window length) output samples and stops then.

I would like to extend this program and combined the FIR filter with a throughput program. I would like to read a block of samples form ADC, filter the input block wise and send the filtered and delayed block to the DAC.

How can I start a new/periodical DMA transfer to the FIR Accelerator, after the output is read and new input samples are written?

Thanks a lot for your answer.

-Thomas

problem with setting SCF

analog@sgaur.hosted.jivesoftware.com — Wed, 14 Oct 2009 20:01:18 GMT

Hello

I am trying to set SCF for ADV7179 of ADSP-BF561 EZ-KIT LIte. After compilation in debug mode and running from idde all works fine, but after compilation in release mode function returns ADI_DEV_RESULT_TWI_LOCKED ( TWI locked in other operationI In debug mode ). I use the next code

adi_int_Init(...);

adi_dma_Init(...);

adi_dev_Init(...);

adi_tmr_Init(...) ;

EnableADV7179() ; // from VideoInOut example

adi_dev_Open( hDevManager, &ADIADV7179EntryPoint, 0, &ADV7179Handle, ADI_DEV_DIRECTION_OUTBOUND,
hDMAManager, Callback, clientHandle, NULL ) ;

adi_dev_Control( ADV7179Handle, ADI_ADV717x_CMD_SET_PPI_DEVICE_NUMBER, ( void* )1 ) ;
adi_dev_Control( ADV7179Handle, ADI_ADV717x_CMD_SET_PPI_STATUS, ( void* )ADI_ADV717x_PPI_OPEN ) ;
adi_dev_Control( ADV7179Handle, ADI_ADV717x_CMD_SET_TWI_CONFIG_TABLE, ( void* )twiConfig ) ;

//twiConfig from example in "ADI_ADV717X DEVICE DRIVER"

u32 err = adi_dev_Control( ADV7179Handle, ADI_ADV717x_CMD_SET_SCF_REG, ( void* ) ADV717x_SCF_VALUE_PAL_BI ) ;

printf( "err: 0x%X\n", err )

Am I missing something?

substitute for accelerometer adxl202

analog@sgaur.hosted.jivesoftware.com — Thu, 27 Aug 2009 08:50:50 GMT

Hello,

Currently I use an accelerometer adxl202 for a poduct of my compagnie. Analog devices makes a transition from adxl202 to adxl213.

I have a probleme with the g-Range of ADXL213 wich is +/-1.2g. I need an accelerometer with at least a g-Range of +/-2g and a duty cycle output.

Is there an accelerometer with this charactéristic? Where can I find him?

Thank you for your answer

Edwin

Is it possible to change the frequency of MCLK while a SigmaDSP is in operation?

analog@sgaur.hosted.jivesoftware.com — Wed, 09 Sep 2009 18:06:01 GMT

Is it possible to change the frequency of MCLK while a SigmaDSP is in operation?

How to include a 'Version Information' Global Variable but ensure it is not eliminated

analog@sgaur.hosted.jivesoftware.com — Thu, 07 May 2009 15:42:38 GMT

I would like to include a 'Version Information' variable into my software libraries, so tried a global variable into the library. Unfortunately, this symbol does not show up in my final application. How I can prevent these global variables to be eliminated?

DSP selection criteria

analog@sgaur.hosted.jivesoftware.com — Sun, 20 Sep 2009 07:54:43 GMT

I have to design a system which should be capable to interfacing 3 megapixel cameras over USB interface with DSP and application is to detect defective parts in a assembly line. I have to use OpenCV library for image processing algorithms.

I am new to DSP design and need to choose which DSP should be best to fit my requirements.

I have selected ADSP-BF535P for this but not sure if this DSP can meet the 3 megapixel USB camera interface.

Any link or technical clarification will be highly appreciated.

Where can I find the latest update for the VisualDSP++ tools?

analog@sgaur.hosted.jivesoftware.com — Wed, 18 Feb 2009 09:55:27 GMT

Where can I find the latest update for the VisualDSP++ tools?

Is there a data sheet for evaluation board EVAL-ADAU1442EBZ ?

randyperkins@randyperkins.com — Fri, 02 Oct 2009 04:07:11 GMT

Hello

Thanks for the assistance.

the FAQ at

http://www.analog.com/en/audiovideo-products/audio-signal-processors/adau1442/products/faqs/CU_faq_SigmaDSP_FAQs/resources/fca.html#ADAU1442_45_46b

and the SigmaDSP Evaluation Boards at

http://www.analog.com/en/embedded-processing-dsp/sigmadsp/products/evaluation-boardstools/sigmadsp_evaluation_boards/resources/fca.html

both list evaluation board EVAL-ADAU1442EBZ,

However I can not locate a data sheet the that gives the specifics of that particular evaluation board.

this page generates an error for me

http://www.analog.com/en/embedded-processing-dsp/sigmadsp/ADAU1442/processors/product.html#ppa_print_table

basically this page only lists 6 data sheets for SigmaDSP evaluation boards

http://www.analog.com/en/evaluation-boards-kits/resources/embedded-processing-dsp/sigmadsp/index.html

while this page lists 8 boards

http://www.analog.com/en/embedded-processing-dsp/sigmadsp/products/evaluation-boardstools/sigmadsp_evaluation_boards/resources/fca.html

one of the missing ones is the one I wanted to study tonight

thanks

rperkins

Regarding part selection of DAC, Amplifier, Filter and analog differential output

analog@sgaur.hosted.jivesoftware.com — Fri, 31 Jul 2009 12:17:39 GMT

Hi,

I am having design requirement for the following:

1. That is DAC 32 Channel,14 bit Parallel input, (0-10)V Analog output. I have seen in your product list. But, i couldn't find Digital to Analog converter chip for DAC 32 Channel,14 bit Parallel input, (0-10)V Analog output. If that is there, please send it to me by immediately or suggest that part number. It is urgent requirements.

2. I have attached my application block diagram. please find the attachments for your reference.

3. I need to choose amplifier for above analog output sections. For this also i need the Analog Devices part number.

4. After analog amplification section, i need to filter the analog signal. There i need to put one 10KHz low pass filter. Please provide Analog devices part number for this also.

5. After filtered the analog output signal, i need to convert into differential output. Please provide Analog devices part number for this also.

Please reply me as soon as possible. Then,only ican start the design quickly.

Thanks and Regards,

N.Magalingam

Hardware Design Engineer-Embedded System

Cornet Technology India Pvt Ltd

Chennai-20

Mobile:+91-9994867369

mono input question

analog@sgaur.hosted.jivesoftware.com — Wed, 16 Sep 2009 01:54:00 GMT

hi,

I am working with a ez-kit lite adsp-21364 and i am taking my input from spdif.As i have understood from the manuals the receive buffer of the sport communicating with the spdif fills with both left and right channel(i use i2s)if the input is stereo and doubles the left channel if input is mono.Is there a way other than DMA and dumping every other channel to have a mono input.I am develloping a core driven aplication that doesn't require both channels.

thanks in advance

SDCards via SPI interface on Blackfins without SDController (BF537)

analog@sgaur.hosted.jivesoftware.com — Fri, 05 Jun 2009 11:13:15 GMT

Is there any code which supports filesystems on SDCards connected via SPI interface?

or only communication to sdcards with spi

regards chris

How do I purchase an EVAL-ADUSB2EBZ (a.k.a. USBi)?

analog@sgaur.hosted.jivesoftware.com — Tue, 28 Jul 2009 16:36:31 GMT

How do I purchase an EVAL-ADUSB2EBZ (a.k.a. USBi)?

How do you compile "initcode" into a .dxe ?

analog@sgaur.hosted.jivesoftware.com — Wed, 01 Jul 2009 20:46:49 GMT

Hi,

I'm using a BF-527 EZ-KIT Lite with silicon revision 0.2

and Visual DSP++ 5.0 with update 6.

There are "init_code" example projects given to us when we installed Visual DSP located in:

$(MY_ANALOG_DEVICES_FOLDER)\VisualDSP 5.0\Blackfin\ldr\init_code\c\ADSP-BF527 EZ-KIT Lite\

such as

ezkitBF527_initcode_ROM-V00.dpj

ezkitBF527_initcode_ROM-V01.dpj

ezkitBF527_initcode_ROM-V02.dpj

How do I successfully compile these projects into a .dxe for "elfloader" ???

When I try to compile them it always complains about not having a "main" entry function, and that is obvious because there is no main.

Do I have to add my own "dummy main" function or is there some compiler switch I am missing in compiling these projects into a .dxe ??

Thanks.

Enhanced PPI External Synchronization problem

analog@sgaur.hosted.jivesoftware.com — Mon, 13 Jul 2009 08:50:56 GMT

Hi all,

We have a project with a basic task to get images from an image sensor to process with a BF548. Since our image sensor board is being designed, to not to waste time waiting for it, I have been trying to get image data from a microcontroller with same clock, frame-sync signals and -some random- image data output.

I am -only- able to get image data from EPPI1, in no frame sync mode, when PPI1_CONTROL = 0x0002180C. In summary, this is the EPPI control register mode for GP0FS with "internal" trigger.

When I try to use external trigger mode with same settings as above, (GP0FS, external trigger; EPPI1_CONTROL = 0x0012184C ) I get no data, even one pixel. I tried all possible clock and sync (POLC and POLS), DMA watermark and dma-packaging combinations without any success.

I also try to get data in GP1FS (EPPI1_CONTROL = 0x0002189C) and GP2FS (EPPI1_CONTROL = 0x0012782C) mode with no success.

Following values I used in my code are

EPPI1 Register settings for GP0FS:
PPI1_CONTROL = 0x0012184C

    EPPI1 Register settings for GP1FS:
PPI1_CONTROL = 0x0002189C
/* # of pxls per line: EPPI_LINE */
{ ADI_EPPI_CMD_SET_SAMPLES_PER_LINE,          (void *)12 },
/* # of empty pixels/line: EPPI_HDELAY */
{ ADI_EPPI_CMD_SET_HORIZONTAL_DELAY,           (void *)0 },
/* # of active pixels/line: EPPI_HCOUNT */
{ ADI_EPPI_CMD_SET_HORIZONTAL_TX_COUNT,     (void *)12 },

    EPPI1 Register settings for GP2FS:
PPI1_CONTROL = 0x0012782C
/* # of pxls per line: EPPI_LINE */
{ ADI_EPPI_CMD_SET_SAMPLES_PER_LINE,          (void *)12 },
/* # of empty pixels/line: EPPI_HDELAY */
{ ADI_EPPI_CMD_SET_HORIZONTAL_DELAY,           (void *)0 },
/* # of active pixels/line: EPPI_HCOUNT */
{ ADI_EPPI_CMD_SET_HORIZONTAL_TX_COUNT,     (void *)12 },

/* # of lines per frame: EPPI_FRAME */
{ ADI_EPPI_CMD_SET_LINES_PER_FRAME,           (void *)18 },
/* # of empty lines: EPPI_VDELAY */
{ ADI_EPPI_CMD_SET_VERTICAL_DELAY,              (void *)0 },
/* # of active lines per frame: VCOUNT */
{ ADI_EPPI_CMD_SET_VERTICAL_TX_COUNT,         (void *)18 },

respectively.

EPPI clock frequency is 100 ms, thus approximately 10Hz.Each cell of logic analyser output is 250ms.

I am using VDSP++ 5.0 and working on ADSP-BF548 EZ-KIT Lite rev 1.4 with silicon rev 2.0. I have disabled keypad and LCD via relative dipswitches. FS3 is pulled down. FS1 is HSYNC and FS2 is VSYNC. Logic analyser output of our sensor-board-emulating-micro is attached. First two pins are clock, others are VSYNC, HSYNC and a start signal I use to trigger microcontroller respectively.

I have examined linux kernel source but could not find anything special ( for my case of course :] ). I also looked at anomalies documents. There are many samples in blackfin\examples for video out but I could not find any for video in. So anyone have an idea or suggestion? Has anyone got any experience or working example for EPPI data-in?

Thanks in advance

Alper

What is the sensitivity of ADXL335 in mg

analog@sgaur.hosted.jivesoftware.com — Fri, 23 Oct 2009 21:20:37 GMT

I go through the datasheet and don't find the decription. can someone tell me what the minimum acceleron in unit:mg does the ADXL335 pick up with 50hz bandwidth?

i appologize if I post at the wrong place.

thanks.

32-bit vs 64-bit performance degradation on Tiger SHARC + 2 more questions.

analog@sgaur.hosted.jivesoftware.com — Thu, 03 Sep 2009 00:42:25 GMT

Hi,

could you please specify what performance degradation I can expect executing my matrix-vector operations where my numbers are float i.e. 32-bit versus 64-bit doubles. I know that SHARC family support 64-bit floats only via floating point emulation library hence execution will be much slower, the question I have how much slower? What sustained performance I can expect i.e. how far from 3.2GFlops pick for 32-bit floats?

Can anyone comment on performance using 40-bit extended precision? Are there any libraries that will support arthementic for such extended precision or the hand crafted assembler is only the option?

Are you aware of BLAS library for Tiger SHARC?

Regards

Adam

Using Thumbwheel driver with VDK

yair@raztek-inc.com — Thu, 24 Sep 2009 00:42:56 GMT

I'm using the ADSP-BF518 EZkit.

The Thumbwheel example I have seen (part of the VisualDSP installation), used the Deferred Callback manager with the Thumbwheel driver (in drivers/rotary/adi_cnt.c).

My application used VDK. I need to generate VDK event upon certain thumbwheel events. Should I use live call backs with that driver, or should I use DCB, as in the examples?

Regard,

Yair

explanations on compiler annotations needed

analog@sgaur.hosted.jivesoftware.com — Wed, 14 Oct 2009 08:49:16 GMT

When I compile the following code

float ftemp, ftemp2=0.0, buf[20];

int i;

for(i=0; i<20; i++){
ftemp = powf(buf[i], 2.0);
ftemp2 += ftemp;
}

with VisualDSP++ 5.0 Update 6 for ADSP-BF527, I have the following compiler annotations (double clicking over the "i" on the for( ) line)

[Info] This loop executes 1 iteration of the original loop in estimated 27 cycles.
[Info] cycle count 27 excludes the cost of the inner function calls and it includes 7 stalls
[Info] This loop's resource usage is:
       //     Group 1             used 19 out of   27 ( 70.4%)
       //     16-bit Instruction used 28 out of   54 ( 51.9%)
       //     32-bit Instruction used   9 out of   27 ( 33.3%)
       //     Store               used   3 out of   27 ( 11.1%)

What does the resource usage mean?

Group 1 + 16-bit + 32-bit + Store = 59 (grater than 27 cycles)

70.4% + 51.9% + 33.3% + 11.1% = 166.7%!!!!

Could someone explain me what this [Info] lines mean?

Thanks

Optimized exception handler -- minimum length of exception?

analog@sgaur.hosted.jivesoftware.com — Tue, 13 Oct 2009 13:16:35 GMT

There is a Blackfin anonomoly that requires the RTS instruction to be a 4 cycles from the start of a subroutine?

Is there a similar restriction on exception handlers?

I am trying to write fast exception handlers

e.g. recent post on why link / unlink used in exception handler that does not call a subroutine

e.g. queried why ssync( ) becomes stop interrupts, ssync, restart interrupts inside exception handler

The sort of situation I could imagine causing a problem is an exception handler where the RETX is around "a pipeline" distance from the start of the exception handler

The minimum exception length (except for RETX) would be save P0, R0, set P0, set R0 value, save R0 value, recover R0, P0, RETX which would be close to being shorter than "the one pipeline" distance. If you thropw a ssync in there, then I think it would be way past that limit

Are there any problems on minimum length?

Thanks

Mike

power up sequence for BF527

analog@sgaur.hosted.jivesoftware.com — Fri, 15 May 2009 12:16:35 GMT

We are designing a low power battery operated portable design. The processor
operating voltages are VDDINT= 1.2V(External), VDDEXT= 1.8V, VDDUSB= 3.3V and
others at the recommended voltages. In our board we want to generate 3.3V
before 1.2V and 1.8V to facilitate power sequencing for the Ethernet Phy.
Please tell me whether the processor needs any specific power up sequence and
whether the processor will operate properly at the conditions mentioned above?
Will the 3.3V coming before the 1.2V and 1.8V affect/Damage the processor?

Display Memory Usage in VisualDSP++

analog@sgaur.hosted.jivesoftware.com — Fri, 25 Sep 2009 18:11:04 GMT

Do you know of an easy way to show the memory usage of a running application in VDSP++ instead of the CPU usage? I assume that the default for the statistical profile tool is the CPU usage...

BF527, otp_write, error 9

analog@sgaur.hosted.jivesoftware.com — Wed, 07 Oct 2009 08:53:23 GMT

Hello,

I am trying to write otp memory, but otp_write-function returns always error code 9 (Attempt to access invalid OTP space). I have tried to write public key pages (0x10 - 0x12) and also inside Unsecured general purpose space (pages 0x01C to 0x0DF). I have tried to write lockbox public key to my own hardware for testing purposes (otp_read works, I was able to read public key area from BF527 evaluation board). In my HW BF527 rev. is 0.2. I cannot test lockbox with my BF527 evaluation board, because it has processor rev. 0.0 (0.2 is required for lockbox).

I have used modified lockbox demo (lockbox_example.c):

u8 au8_public_key[ ] =

{

0xA6,0xC0,0x9B,0x8A,0xA0,0x5D,0x1D,0xBB,0x76,0xCE,0x39,0x1E,0x00,0x3D,0x19,0x43,

0xF2,0x8A,0x36,0x69,0x03,0x00,0x00,0x00,0x1B,0x25,0x2E,0xCD,0xF7,0x6E,0x7F,0x16,

0x0F,0xE7,0x05,0xB0,0xE1,0xF1,0xD4,0x41,0xC8,0x90,0x7A,0x5F,0x01,0x00,0x00,0x00

};

s32 main( s32 argc, s8 *argv[] )

{

unsigned long ul_error = 0;

u64 data;

u32 page;

int byte;

u32 (*otp_read)(u32 page, u32 half, u64 *page_content) = ( void* )0xEF00001A;

u32 (*otp_write)(u32 page, u32 half, u64 *page_content) = ( void* )0xEF00001C;

u8 *pu8_p;

int index = 0;

pu8_p = ( u8* )&data;

/* Initialize system services. */

InitSystemServices();

// Test write to page 0x50

data = 0x12345678;

ul_error = otp_write( 0x50, 0, &data );

if( 0 != ul_error )

{

printf( "OTP write error: 0x%X\n", ul_error );

}

// Write public key

for( page = 0x10; page <= 0x12; page++ )

{

// Lower half

for( byte = 0; byte < 8; byte++ )

{

*( pu8_p + byte ) = au8_public_key[ index++ ];

printf( "0x%02X,", *( pu8_p + byte ) );

}

ul_error = otp_write( page, 0, &data );

if( 0 != ul_error )

{

printf( "OTP write error: 0x%X\n", ul_error );

}

// Higher half

for( byte = 0; byte < 8; byte++ )

{

*( pu8_p + byte ) = au8_public_key[ index++ ];

printf( "0x%02X,", *( pu8_p + byte ) );

}

ul_error = otp_write( page, 1, &data );

if( 0 != ul_error )

{

printf( "OTP write error: 0x%X\n", ul_error );

}

printf( "\n" );

}

hppci device driver

analog@sgaur.hosted.jivesoftware.com — Wed, 28 Oct 2009 02:03:41 GMT

Hello, I have a HPPCI Emulator, but I can`t use it because of the lack of driver.

Can you help me?

thanks

Making changes at run time

analog@sgaur.hosted.jivesoftware.com — Fri, 23 Oct 2009 07:06:29 GMT

Hi,

I'm evaluating at the moment the ADSP-21469 for audio application. Are there any possibilities to make changes at run time of the dsp, e.g. changing coefficients for IIR an FIR filters?

Best Regards,

Marc

Switch/Case compiler error?

analog@sgaur.hosted.jivesoftware.com — Thu, 20 Aug 2009 19:35:17 GMT

I am using VSDP 5.0 and ADSP 21368. In the following code snippet the if/elseif method works, and rthe switch/case method creates a jump(0x0).

Any clues?

void setPin (PSD_PIN_NAME pin)
{
#if 0
// DEBUG!
if (pin == TEMP_CONV)
sysreg_bit_set(sysreg_FLAGS, FLG5);
else if (pin == TEMP_FRAME)
   sysreg_bit_set(sysreg_FLAGS, FLG6);
else if (pin == POINTER_EN)
   sysreg_bit_set(sysreg_FLAGS, FLG7);
else if (pin == LEVEL_CS)
   sysreg_bit_set(sysreg_FLAGS, FLG8);

return;
#endif

switch (pin)
{
case TEMP_CONV:
    sysreg_bit_set(sysreg_FLAGS, FLG5);
    break;

case TEMP_FRAME:
sysreg_bit_set(sysreg_FLAGS, FLG6);
break;

case POINTER_EN:
sysreg_bit_set(sysreg_FLAGS, FLG7);
break;

case LEVEL_CS:
sysreg_bit_set(sysreg_FLAGS, FLG8);
break;

default:
break;
} // end switch
}

I can't control any of the knobs or sliders in my SigmaStudio project. What's wrong?

analog@sgaur.hosted.jivesoftware.com — Wed, 29 Jul 2009 19:14:07 GMT

I can't control any of the knobs or sliders in my SigmaStudio project. What's wrong?

Watchpoint register operation -- Processor hardware challenge

analog@sgaur.hosted.jivesoftware.com — Tue, 21 Jul 2009 03:20:48 GMT

Background to question

As academics, we look at new techniques for developing analysis tools for embedded systems. We are publishing in the area of race condition analysis -- e.g. fights for data access between VDK threads.

In the IEEE Software magazine special issue (May / June 2009) on testing of embedded systems we discussed hardware code instrumentation showing that the Blackfin has many desirable features in this area that are not present in other processors.

Software instrumentation of code is always an option, but hardware instrumentation is faster. People are researching new architectural features to solve the problem, but we have shown that Blackfin already has these features. We showed how to use the Blackfin trace buffer to handle code coverage issues for testing and the data watch registers to handle data race conditions.

Basically, we set up the data watch registers to watch a data location. When the match arises, we check to see if the thread has all the correct locks for accessing this memory location. We would like to see an exception triggered on the data match, but the hardware triggers an emulation, and we have to live with that

Software instrumentation slows the code down by 200 times (IBM thread checker for example) so even jumping in and out of emulation mode could actually be faster. Even if not, we could simulate the performance of a "perfect" Blackfin.

We have a background GUI which recognizes when VDSP switched into emulation mode after a data watch match. The GUI then changes the watch control, status and count register, and causes the processor to start again. With the data watch counter modified, the instruction re-eexcutes without causing a second data match.

Code seems to be working, but we are now trying to optimize how fast the GUI can restart the processor after doing the data arace analysis.

QUESTION 1

When VDSP is thrown into a data watch emulation, VDSP prints out a message on the console screen of the form

DATA WATCH 0 AT (PROGRAM) ADDRESS XXX AT (MEMORY) ADDRESS YYY

Which means that this operation consumes the time for a print, 3 symbol table look up and 3 access to the blackfin over the JTAG to access 3 registers inside VDSP.

This consume 63 ms (excluding the time for getting in and out of VDSP)

So the question is -- what do I need to do so that I can cause VDSP to jump round this print to console statement -- I would prefer an answer that avoided NDA, a patch for example

QUESTION 2

When the data watch emulation is thrown, we need to do a lot of analysis to see if the data match could lead to data race conditions (lets not worry about the details)

This would mean that inside the GUI many accesses to Blackfin memory locations are needed -- too slow over the JTAG. Therefore I am looking for a way around this JTAG access.

Attempt 1 -- unsuccesful

Fix the watch control, status and count register inside the GUI, copy RETE into RETX, and set the RETE to point to the start of an exception handler (which save and recovers any registers). Inside the exception handler, do all the data analysis we want by directly access memory location rather than over the JTAG for speed reasons.

I prefer to use an exception rather than interrupt as data matches could be occuring inside an interrupt, but are less likely inside an exception

When the exception handler exits, we return to the address that was originally stored in the RETE and (in principle) the code continues.

It works the first time a data watch match occurs but not the second time. The error message is that I have accessed a system register while in user mode. The only system register I am accessing during the exception handler is the RTX instruction itself

If this approach would crash the first time, I would not be upset,as the crash would match expected behaviour. However the fact that it crashes the second time suggests I am missing some minor detail which, if fixed, would allow the approach to work.

I can put sysreg_write(reg_RETX, 0x20) in my main( ) which says to me that I am starting out in supervisor mode -- so at what point did I switch to user mode and why?

Attempt 2 -- apparently successful

I presumed that the error in the first attempt was due to the fact that I was getting into the exception routine via the Emulation mode without properly setting ILATCH IPEND etc. (which you can't do inside VDSP)

So I tried the following

Set up some code to crash the processor by a data access error

_SetCrash:

Save P0

P0 = 1;

[P0] = R0;

Set up some code to access location "desired address" which is being monitored by the data watch unit

_CauseMemoryMatch:

P1 = desired address

[P1] = R0;

nop;

etc

RTS

When CauseMemoryMatch is called and the memory match occurs, the processor swicthes into emulation mode. The GUI saves the RETE to location SAVE_RETE on processor, and sets RETE to SetCrash and restarts the processor

The code _SetCrash causes an exception

The exception handler checks to see if RETX is SetCrash + 4 -- and then does data watch code stuff, before setting RETX to the value stored in SAVE_RETE

I will fix the exception handler to recover P0 later -- not needed at the moment as the match is happening inside a subroutine so P0 is volatile.

When the exception handler exits, the processor returns and re-executes the instruction inside CauseMemoryMatch. This does not cause a new data match as the watch counter has been reset.

Seems to work -- so the questions are

(A) is it really working or is some nasty hardware feature going to catch me out later

(B) s there a better (faster and reliable) way of getting out of the data watch emulation mode and into some code running on the processor where I can perform data analysis before restarting the original code.

MJPEG solution ?

analog@sgaur.hosted.jivesoftware.com — Tue, 13 Oct 2009 07:23:39 GMT

Hello,

I am looking for a solution to encode 16 video channels in MJPEG

Do you provide this type of solution ?

Thanks

How do I get the number of bytes read from UART DMA?

analog@sgaur.hosted.jivesoftware.com — Mon, 19 Oct 2009 12:26:49 GMT

Is there a way to read a register and get the number of bytes that the UART DMA has in the receive buffer. I have multiple message formats that I am reading and they are different sizes. I have headers on the messages so I know which message I receive when I get into the uart isr. I would like to tell the UART DMA engine that I want any size message instead of assigning a size to pCUART0RX.

// UART0 receiver is configured in DMA mode
(*pUART0RXCTL) = 0; // clears the UART receive control register

*pIIUART0RX = (unsigned int) &uart_receive_message[0]; // address for DMA
*pIMUART0RX = 1; // modifier
*pCUART0RX = UART_receive_count; // count

need to know a certain syntax

analog@sgaur.hosted.jivesoftware.com — Wed, 22 Jul 2009 08:45:05 GMT

hello

i am working in ADSP-TS201 and programming it by c language and need to know if there a syntax by c to test bits in registers or i should do it by assembly

thank you

I have an ADZS-BF548 EZ-KITand I would like to evaluate the Media Player

analog@sgaur.hosted.jivesoftware.com — Mon, 31 Aug 2009 16:13:01 GMT

I have an ADZS-BF548 EZ-KITand I would like to evaluate the Media Player. How do I go about this?

BF548 Audio Loopback and LCD Display Merging Problem

analog@sgaur.hosted.jivesoftware.com — Tue, 06 Oct 2009 04:18:39 GMT

Hi all,

We are using BF548 and connecting the audio part and LCD display and want to display the spectrum on the LCD screen.

What we have done:

1. Run Audio-loopback example, MIC-IN / Audio in sound and play it through the MICROPHONE.

2. Display some generated SIN wave spectrum(time and frequency) on LCD display.

3. Combined Audio-loopback and Display projects in one, but not working.

Difficulties we met:

1. can not controll two drivers (1. audio->AD1980->Sport0 using DMA channel 0(sport0 RX) and DMA channel 1(sport0 TX) and 2. LCD display-> EPPI0-> DMA channel 12 (TX and RX) ) at the same time

2. we leant example named " VideoinLcdout" in BlackfinSDK-3.11 folderpackagewe think there maybe something relating to the DMA priority so we change the priority in the following way,

adi_dma_SetMapping(ADI_DMA_PMAP_SPORT0_RX,ADI_DMA_DMA12);

adi_dma_SetMapping(ADI_DMA_PMAP_EPPI0, ADI_DMA_DMA0);

but it still not working. what we found in "ADSP-BF54x Blackfin® ProcessorHardware Reference (Volume 1 of 2) " P262 and P263 saying: the sport0 we are using belongs to DMA controller 0, while EPPI0 belongs to DMA controller 1. And it seems to us that DMA controller 0 has the priority over DMA controller 1, so maybe it's the reason why Audio always play but Display not working.

Btw, In the main funcition we want to run two funcitons 1 audio() and 2 displaypic() sequencely but can only play audio loopback. Only if we close the audio() by using adi_dev_Close(AudioCodecDriverHandle) that we can display on screen.

Also, here is the code segment:

-------------------------------------------------------------------------------------

/* Audio AD inbound buffers dataflow handling */

nadi_dev_Read(AudioCodecDriverHandle, ADI_DEV_1D, (ADI_DEV_BUFFER *)&InboundBuffer0)

nadi_dev_Write(AudioCodecDriverHandle, ADI_DEV_1D, (ADI_DEV_BUFFER )&OutboundBuffer0)

nadi_dev_Control(AudioCodecDriverHandle, ADI_DEV_CMD_SET_DATAFLOW, (void *)TRUE)

// adi_dev_Close(AudioCodecDriverHandle);

/* Display Ping-Pong buffers dataflow handling */

nadi_dev_Control(LCDDriverHandle, ADI_DEV_CMD_SET_DATAFLOW_METHOD, (void*)ADI_DEV_MODE_CHAINED_LOOPBACK )

nadi_dev_Write(LCDDriverHandle, ADI_DEV_2D, (ADI_DEV_BUFFER *)PingBuffer)

nadi_dev_Write(LCDDriverHandle, ADI_DEV_2D, (ADI_DEV_BUFFER *)PongBuffer)

nadi_dev_Control(LCDDriverHandle, ADI_DEV_CMD_SET_DATAFLOW, (void *)TRUE)

----------------------------------------------------------------------------------------

So anyone have any idea how to use two driver at the same time??? Please help us, really appreciated.

xiaofei

Pin behavior of BF526 at hibernate state

analog@sgaur.hosted.jivesoftware.com — Tue, 27 Oct 2009 09:05:53 GMT

Hello,

In my application , the DSP is supposed to enter the hibernate state to save power. In the datasheet, appears a "mysterious" sentence stating that

"Since Vddext and Vddmem can still by applied in this mode,all of the external pins three-state,unless otherwise specified". Can someone please explain this ?. Does it mean that I can set the actual value of each pin, and if I don't, then it will three-state ?. If so, where does this specification takes place.

Regards,

Vladimir Kogan

SM2602 CODEC Driver for the ADSP-BF518 EZkit

yair@raztek-inc.com — Tue, 22 Sep 2009 22:53:10 GMT

Hello,

As my application needs that CODEC (that is why I bought this board), I browsed through the source code of the drivers in the VisualDSP installation, and found that there is a driver for this CODEC (a good step).

However, I did not find any documentation (PDF) for that driver, nor any example on how to use it with the board.

Can someone provide me with some documentation on that driver + and example program that ilustrates its usage?

Thanks in advance,

Yair

How the 2146x's IIR/FIR/FFT accelerators fit into RT signal processing

analog@sgaur.hosted.jivesoftware.com — Tue, 21 Jul 2009 17:53:37 GMT

Hey guys!

I was wondering if anyone had any insight to share about the intended usage-model of the HW accelerators? The concept of off-loading MIPs is smart and makes sense as a bullet-point, but it's not obvious to me how to leverage them in a real-time system.

For example, let's consider a classic audio system with block-based processing:

In this system, we have a chained DMA that periodically pulls in 32-samples from an ADC. When we get the DMA-complete interrupt, we do two things: 1) update some pointers so we can handle the new data, then 2) raise a lower priority interrupt [USER0, e.g.] where we do our audio processing.

When we RTI from our DMA-complete ISR, we vector to the signal processing thread [ISR]. Being a real-time system, we need to complete this processing and return to the while(1) loop in main() before the next DMA completes. It is HERE where the FFT's and filters live... in the "ProcessAudioBlock()" subroutines.

In my experience, this processing is usually very serial... e.g., maybe you start with a low-pass filter on the input, then maybe you do some bass-mgt (more filters), then you finish with some more filtering before outputting to a DAC. You necessarily have to do these in 1-2-3 order.

In such a archetypal SHARC system, where there's little parallelism in the signal-flow, how can we leverage these accelerators? Does anyone have an alternative architecture/thread-priority to the one I presented above? Just thinking out loud here, but if latency isn't a big concern, perhaps introducing a software/data 'pipeline' may provide an opportunity to use these.... <squint> ... o_0 ... <considers complex state-table> ... <head explodes>

Beuller?

Has anyone used the BF2DGL with VDK? How was glutMainLoop() placed?

analog@sgaur.hosted.jivesoftware.com — Thu, 15 Oct 2009 22:08:42 GMT

Has anyone used the BF2DGL with VDK? How was glutMainLoop() placed?

I've used the demo that came with the library but it was not VDK based.

Thanks,

Scot R

Priority inheritance mutex

analog@sgaur.hosted.jivesoftware.com — Wed, 11 Nov 2009 10:07:13 GMT

This thread would be better placed in the VisualDSP++ Development Tools category, and has been moved here:Priority inheritance mutex

Thank you.

Guidence required!!!

analog@sgaur.hosted.jivesoftware.com — Fri, 24 Jul 2009 19:25:56 GMT

I am doing b.e electrical and electronics from bits-pilani , india.
I have just completed my second year.
I had a course on signal and systems(fourier, laplace, sampling etc.) in my fourth semester.It has aroused my interest in dsp field.
Can anyone here guide me on how to proceed with my education in this field so that i could have both theoritical and practical knowledge in the field.
Also is it necessary to choose a specific field such as image, audio , video processing right from the beginning or should i take a course on general dsp first?
And my last question is directed towards indian members on this forum.I know of the huge scope of dsp outside. Does India has the same scope for a career in dsp field..

compress and decompress in VisualDSP++

analog@sgaur.hosted.jivesoftware.com — Wed, 30 Sep 2009 15:12:40 GMT

Hi,

I have a large binary file (about 6MB) that i would like to compress and include in VisualDSP++ as a binary file .

when application boots up i would like decompress same file.

Is there any tool to compress and decompress in VisualDSP++ ?or any better way to do this?

Thank You,

Sjoshi

ADI TWI driver problem running in release mode

analog@sgaur.hosted.jivesoftware.com — Fri, 25 Sep 2009 13:31:52 GMT

Hello,

Are there any known problems running the ADI TWI drivers in release mode? I call adi_dev_SequentialIO(twiHandle, ADI_DEV_SEQ_1D, (ADI_DEV_BUFFER *)&pSeq[0]);...), and it "seems" to return with Result=ADI_DEV_RESULT_SUCCESS, but the program does not proceed any further from that point. Nothing happens in my callback either (good or bad). All is fine in debug mode. I am on a BF548 running VDK using VDSP++ 5.0 update. Any suggestions?

Thanks,

Scott

Category of VisualAudio Discussion

analog@sgaur.hosted.jivesoftware.com — Sat, 25 Jul 2009 01:15:49 GMT

Hi,

VisualAudio is a very good program for developing audio application using ADSPs. A separate category for it must be very popular.

Thanks,

Zwone.

How to make the processor, to boot from different locations of flash?

analog@sgaur.hosted.jivesoftware.com — Sat, 20 Jun 2009 04:06:04 GMT

I am using ADSP 21368 based custom board, I need to flash multiple applications (at different locations) on to the flash memory on my board and boot the processor from which ever location using some switching process. Flash writing part can be done. I want to know, how to make the processor, to boot from different locations of flash.

Thanks in advance.

Internal Voltage regulator

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Apr 2009 10:30:45 GMT

Can I use the internal voltage regulator when VDDext = 1.8V?

I've got 'cc1458: Fatal error: could not obtain license'. What is the problem with my license?

analog@sgaur.hosted.jivesoftware.com — Wed, 04 Mar 2009 14:57:04 GMT

I have valid VisualDSP++ license which comes with my ADSP-21262 EZ-Kit Lite. When I tried to compile the example from Blackfin tutorials, I've got following error;

cc1458: Fatal error: could not obtain license

1 catastrophic error detected in the compilation of ".\dotprod.c".

Compilation terminated.

What is happening on my VisualDSP++ license?

Increasing the tap size of FIR filters

analog@sgaur.hosted.jivesoftware.com — Wed, 26 Aug 2009 01:10:39 GMT

I am currently implementing AEC-algorithms for my FYP onto EZKIT BF533. However, I need to increase my tapsize to 1024 (currently, mine is at 64-256).What are the possible ways I can finetune it to increase my tapsizes to 1024? Thanks!

user interfaces on graphical LCD

analog@sgaur.hosted.jivesoftware.com — Thu, 24 Sep 2009 15:46:14 GMT

Hi ADI Support,

for creating a graphical user interface on an LCD connected via PPI the ADI website suggests CPEG from Swell Software. Are there also from ADI any tools available?

Regards

Thomas

bf526 NFC how to DMA spare bytes?

analog@sgaur.hosted.jivesoftware.com — Thu, 29 Oct 2009 09:25:02 GMT

Hi,

I'm working on a flash driver for our platform using bf526 with a NAND chip, 2048 bytes pages + 64 bytes spare area = similar to the EZ-board.

Since we try to make our code tight there is a couple of questions regarding how to work efficient with the NFC and DMA:

When writing:

Looking at the docs & example driver I can't find an example of using DMA to write to the spare area.

Is there a (good) way to use DMA to write the 64 spare bytes?

For reading:

It looks like the example reads a 256 bytes offeset page to read the spare bytes.

Same as above, is there a way to read just the 64 spare bytes using DMA???

best

Having difficulty accurately stepping through the code when external interrupts are applied

analog@sgaur.hosted.jivesoftware.com — Mon, 11 May 2009 09:14:08 GMT

I am seeing that use of the Step Into and Step Over results in the cursor not moving through code at all when I apply external interrupts. If I turn off the external interrupts, I can step through the code accurately. How I can resolve this?

I downloaded the evaluation version of one of your software modules. What are it's limitations?

analog@sgaur.hosted.jivesoftware.com — Mon, 31 Aug 2009 16:52:28 GMT

I downloaded the evaluation version of one of your software modules. Which features are missing from it?

Is the Green Hills Blackfin Processor development suite going to replace the VisualDSP++ suite?

analog@sgaur.hosted.jivesoftware.com — Tue, 10 Feb 2009 10:43:19 GMT

Is the Green Hills Blackfin Processor development suite going to replace the VisualDSP++ suite?

Starting audio programming with Blackfin processors

analog@sgaur.hosted.jivesoftware.com — Fri, 03 Jul 2009 12:17:03 GMT

Hi,

I would like to learn to develop audio software for the Blackfin processor. However so far I have only managed to get the talkthrough examples working! I have only recently begun to learn about audio processing, mainly by using the open source PortAudio API on Windows, in C. This is an easy to use API, with both blocking and non-blocking (callback) mechanisms for providing audio I/O. I have written a simple WAV player program that implements audio mixing, a 3-band equalizer and seeking in the audio buffer.

I want to know how I can apply what I have learned in Portaudio onto the Blackfin platform, for example: how is audio processed in the Blackfin, does it also use callbacks? How can I load a WAV file into memory on the Blackfin (I'm sure it can't be as easy as fopen, fread, malloc?) And how can I use the buttons on the Blackfin for user input, rather than scanning the keyboard for input as in Windows?

If anybody can provide some advice (or example code,books, tutorials etc) on moving from Windows C programming to Blackfin C programming, it would be really appreciated. I have a BF-535 EZ-KIT, but may soon upgrade to a BF-537, if I can make progress :-) . Many thaks for your help.

Best regards,

Daire

Will an airport scanner damage my EZ-KIT or emulator?

analog@sgaur.hosted.jivesoftware.com — Wed, 03 Jun 2009 11:01:41 GMT

I am traveling overseas and need to take my ADZS-BF533-EZLITE and ADZS-HPUSB-ICE. They are both packed in my carry on luggage and I want to know if the X-Ray scanner at the airport will effect the EZ-KIT or ICE?

Reducing Noise on an ADXL345

analog@sgaur.hosted.jivesoftware.com — Tue, 15 Sep 2009 04:04:43 GMT

I'd like to measure some relativly low-frequency, low-intensity signals (rotations at less than 25 Hz), but there's a lot of strong vibrations (High frequency noise) in the environment my device is in. Is it possible to set a low pass filter in the ADXL-345?

If so, is it also possible to oversample? Say, measure at a frequency of 400 Hz, while the low pass filter cuts out noise above 25 Hz.

I didn't see anything in the datasheet about setting filters, so my guess is that I'm SOL. I suppose I could do all of this in software on a DSP, but I'm trying to target a low-power, low-feature microcontroller.

Thanks for your help!

BF518 GRIO input and output driver

analog@sgaur.hosted.jivesoftware.com — Wed, 21 Oct 2009 03:30:09 GMT

The ADSP-BF51x Blackfin Processor Hardware Reference

on page 9-15:

"Once the input driver of a GPIO pin is enabled, the GPIO is not allowed to operate as an output anymore. Never enable the input driver (by setting PORTxIO_INEN

bits) and the output driver (by setting PORTxIO_DIR bits) for the same GPIO."

on page 9-19:

When the GPIO’s input drivers are enabled while the GPIO direction registers configure it as an output, software can trigger a GPIO interrupt by writing to the data/set/toggle registers. The interrupt service routine should clear the GPIO to acknowledge the request."

Why requirements contradict each other?

Access to VDK parameters at program run-time

analog@sgaur.hosted.jivesoftware.com — Fri, 07 Aug 2009 18:44:57 GMT

Hello,

I was wondering if there is a way for my program to find out one of the VDK parameters at runtime? Specifically, I want my program to keep an eye on the stack usage for each of its thread stacks, and warn me if they are getting close to being full and overflowing. For example, I have a thread with a stack size of 512 (as specified in the vDSP Kernel tab), and want my program to know this value (512) without me having to hard code it into the source code. Is there a way to do this?

Thanks !

Why is the Addr0 pin missing?

analog@sgaur.hosted.jivesoftware.com — Thu, 09 Apr 2009 05:58:26 GMT

Why is the Addr0 pin missing on Blackfin Processor EBIU?

ZLIB for LDR compression

analog@sgaur.hosted.jivesoftware.com — Wed, 21 Oct 2009 15:08:48 GMT

I would like to use compression to make our LDR file smaller to save both boot time and space since we are booting off a host microntroller. However, I notice that the ZLIB dxe that is added to the LDR is about 125kB! This about half the size of our application code. Shouldn't the decpmression library be more lightweight than this?

Regards

Jeff Watson

USB_RSET and USB_VREF pin in BF526 USB

analog@sgaur.hosted.jivesoftware.com — Thu, 30 Jul 2009 07:37:54 GMT

hi, does anyone know what is the function of USB_RSET and USB_VREF pin in BF526 USB, how to connect these pins? thanks!

SHARC 2146x SPI Slave Booting

analog@sgaur.hosted.jivesoftware.com — Tue, 18 Aug 2009 18:49:38 GMT

Is EE-177 also applicable to SHARC 2146x processors? I want to make sure I start my design off correctly.

I'm not using OTP memory. Do I reallly need to power VDDOTP?

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Apr 2009 15:26:33 GMT

I don't intend to use OTP memory at all. Do I need to provide the 2.5V to VDDOTP and VPPOTP? If so, why?

What are the differences between the ADAU1442, ADAU1445, and ADAU1446 SigmaDSPs?

analog@sgaur.hosted.jivesoftware.com — Thu, 23 Jul 2009 19:35:35 GMT

What are the differences between the ADAU1442, ADAU1445, and ADAU1446 SigmaDSPs?

Where is the C source file which defines VDK functions such as CreateThread() in VisualDSP++?

analog@sgaur.hosted.jivesoftware.com — Thu, 05 Feb 2009 12:36:33 GMT

Where is the C source file which defines VDK functions such as CreateThread() in VisualDSP++?

Can I add my own shortcut keys within the IDDE?

analog@sgaur.hosted.jivesoftware.com — Mon, 25 May 2009 15:57:22 GMT

Can I add my own shortcut keys within the IDDE?

Why I cannot use the stadnalone debug agent to debug all Blackfin and Sharc processors

analog@sgaur.hosted.jivesoftware.com — Wed, 21 Oct 2009 11:39:59 GMT

This thread would be better placed in the VisualDSP++ Development Tools category, and has been moved here: Why I cannot use the stadnalone debug agent to debug all Blackfin and Sharc processors

Thank you.

kAPIUsedfromISR - What is the Value Information

analog@sgaur.hosted.jivesoftware.com — Thu, 06 Aug 2009 19:56:37 GMT

In our application we are getting Kernel panic messages. Here is the three bits of information we receive.

Kernel Panic
Info0: 0x00000003 (panicCode = ISRError)
Info1: 0x80000041 (SystemError = kAPIUsedfromISR)
Info2: 0x00000180 (value)

What does the 0x180 for the value represent?

Can we find out which API was called or how do we find the address of the VDK API function we called to generate this?

efficient way to calc RMS of 24bit samples

analog@sgaur.hosted.jivesoftware.com — Thu, 05 Nov 2009 14:45:15 GMT

Hi !

I'm looking for an efficient way to calc the RMS of a series of n-samples(24bit) with my BF537.

if have troubles to calc the sum of x^2 and store it because i need at least 64bit-and more if i have an large buffer of samples.

Is there any efficient method known?

is it better to do it by Xrms^2=mean(x)^2+stdDeviation^2 - cost me to loops?

regards chris

in addition

i have observed that define a var as unsigned long long (for u64) dont produce the wanted code to multiply two 32bit vars

or is the u64-value in debug window(locals) not correctly displayed ??

unsigned long long measureCH2=0;

int currInSample[4];

measureCH2 += currInSample[1]*currInSample[1]; /* get the square value */

produces:
[FFA01504] R2 *= R2 ;
[FFA01506] R5 = R2 >>> 31 ;
[FFA0150A] R3 = [ FP + -140 ] ;
[FFA0150E] R6 = [ FP + -136 ] ;
[FFA01512] R2 = R2 + R3 ( NS ) ;
[FFA01516] CC = AC0 ;
[FFA01518] R3 = CC ;
[FFA0151A] R6 = R5 + R6 ( NS ) ;
[FFA0151E] R3 = R6 + R3 ( NS ) ;
[FFA01522] [ FP + -140 ] = R2 ;
[FFA01526] [ FP + -136 ] = R3 ;

Underlying rounding in matmmlt_fr16

analog@sgaur.hosted.jivesoftware.com — Tue, 11 Aug 2009 23:41:00 GMT

Question about the rounding process in matmmlt_fr16. What type of rounding is done in this routine when 32-bit negative numbers must be rounded to 16 (toward zero, or away from zero)? If rounding is done toward zero, is there a way to modify this, either through choice of libraries or through compiler options?

Thanks,

Dana

Clock frequency in VDK

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Apr 2009 09:24:03 GMT

I am using a Core Clock, CCLK = 400 Mhz ,and System Clock, SCLK =120 Mhz. In the VDK kernel tab, I program the System "Clock Frequency" to 150 Mhz. I have a thread with the following code:

while(1)
{
VDK_sleep(2500);
flash_LED();
}

With these settings, the LED was flashing quite often (fast flashing). But when i changed the Kernel tab variable, system clock frequency to 400 Mhz, I see the same LED flashing slow. Do you know why?

Connect adsp-bf533 ez-kit lite to LPT

analog@sgaur.hosted.jivesoftware.com — Wed, 09 Sep 2009 12:20:39 GMT

i have adsp-bf533 ez-kit lite and adsp-bf533/561 extender please help to connect LPT port

Why do i receive, "The serial number has already been used and can be installed only once" when entering a Test Drive license?

analog@sgaur.hosted.jivesoftware.com — Mon, 19 Jan 2009 14:03:23 GMT

I registered my details at the Analog website for a free Test Drive license number but when I try to enter this license number into VisualDSP++ I receive the following message - The serial number has already been used and can be installed only once. Why do I receive this error message and how can I resolve my problem?

PPI with TV display

analog@sgaur.hosted.jivesoftware.com — Wed, 01 Jul 2009 11:28:54 GMT

I m using custom 533 board, in that i ve used ITU 565 display.

i ve written the PPI driver, and I can see the picture in TV.

I have used MDMA, and Discriptor mode is enabled. (display buffer-->line buffer)

while the picture display, I can see some flickering. at the left edge of the display, like some small lines appear and disappear.

Is the information is enough?

how to check this?

EZKIT-21369

analog@sgaur.hosted.jivesoftware.com — Thu, 15 Oct 2009 05:51:27 GMT

The default sampling rate for DAC is 48kHz. How to modified to 192kHz or 96kHz?

EVAL-ADUSB2EBZ (USBi) PC Requirements

analog@sgaur.hosted.jivesoftware.com — Mon, 19 Oct 2009 20:10:49 GMT

The USBi uses a Cypress Semiconductor EZ-USB FX2 (CY7C68XXX) USB microcontroller to interface with the computer's USB port. It is compatible with USB 2.0, but is not compatible with USB 1.1 or USB 1.0. Please make sure that you have a USB 2.0 port on your computer before purchasing a SigmaDSP evaluation board.

VBUS Level Indicator

analog@sgaur.hosted.jivesoftware.com — Wed, 29 Jul 2009 04:57:34 GMT

HI ,

what does USB_OTG_DEV_CTL registers  VBUS1-0 Level Indicator indicate.
Where can i find information with regards to VBUS1-0.

I would like to know if there is some register to check the status of VBUS on Bf54x and Bf52x.

Thanking you 
With regards

ADV7393 test code

analog@sgaur.hosted.jivesoftware.com — Wed, 12 Aug 2009 09:00:42 GMT

Hi,

we are designed uClinux based blackfin537 board with audio,adc,camera&video encoder.

we are using adv7393 video encoder.The problem is in TWI configuration for ADV7393 encoder.

I am attached the adv7393 internal test pattern generation code.can you tell me the way of my configuration is right.

I am not getting any output.

Regards,

Suresh kumar p,

ADI-DSP Lab,

IIT Madras.

BF526 v0.1 Bootrom fails with bootrom.assert.default during preboot

analog@sgaur.hosted.jivesoftware.com — Thu, 18 Jun 2009 01:53:44 GMT

We've got BF526 V0.1 samples, and unable to bood any of them from NOR flash. After hours of debugging i've discovered that preboot fails to what looks like bootrom.assert.default. Unfortunately there's no accessible BF526 bootrom V3 sources or dxe to know see the symbols. Please note that OTP in those samples is unchanged. Also -- if i run "0xef000008" function with 0x20000000 in r0 the blackfin manages to boot correctly, this proves that LDR is valid in flash... What can be done? Where can i find BF526 bootrom V3 dxe and /or sources?

Please help desperate coder

Extra Clocks from the SPI Port in DMA Modes

analog@sgaur.hosted.jivesoftware.com — Thu, 22 Jan 2009 22:25:27 GMT

I am using an ADSP-BF533 in SPI Master Mode and am having trouble when I use DMA to move data. Specifically, no matter what I do, the SPI seems to continuously issue clocks after the DMA has completed. Am I doing something wrong?

Connecting digital camera and graphic LCD to TS201 EZ-KIT Lite

analog@sgaur.hosted.jivesoftware.com — Thu, 25 Jun 2009 19:45:14 GMT

Hi!

I want to connect the digital camera and graphic LCD to LVDS Link Ports of TS201 EZ-KIT Lite. Does somebody know how to do that? What ways are there? Unfortunately, I haven't found the suitable information in Internet.

Many Thanks.

PLL register setting in XML Blackfin BF52x and BF54x

analog@sgaur.hosted.jivesoftware.com — Wed, 10 Jun 2009 14:03:19 GMT

What is the alternative way to set PLL register during emulation as it is not possible to set PLL with XML

showing data memory full after calling fir filter function for 4k samples

analog@sgaur.hosted.jivesoftware.com — Fri, 26 Jun 2009 16:48:30 GMT

I am using adsp-21368 platform with vdsp++5.0 envirinment , after calling fir function for 4k data , msg diplaying full memory !!

my simple fir example ........

fir

##include <filter.h>

##define TAPS 60

#float x[4000], y[4000];

#float pm coeffs[TAPS]; /* coeffs array must be */

# /* initialized and in PM memory */

#float state[TAPS+1];

#int i;

#for (i = 0; i < TAPS+1; i++)

# state[i] = 0; /* initialize state array */

#fir

#fir (x, y, coeffs, state, 4000, TAPS);

# /* y holds the filtered output */

Here two array x[4000] and y[4000] , is it possible to make single array whose input replace with output ?

so i can make filtering of 4000 samples !!

Ashok Majee

i have a problem with the timer would any one help me

analog@sgaur.hosted.jivesoftware.com — Fri, 24 Jul 2009 09:46:48 GMT

i am working on ADSP-TS201 and i was just checking the operation of the timer as i will need it in a certain application and i write this code and checked the assembly language in the assemble everything is okay but i still don't know why it doeasn't work

/*****************************************************************************
* testing.c
**************************************************************************/

#include<sysreg.h>

#include<stdio.h>
#include<defts201.h>

#include<builtins.h>

int main(void)
{
unsigned int t;
unsigned int x;
int i;

__builtin_sysreg_write(__INTCTL,0x00000000); // disable the timer

__builtin_sysreg_write(__TMRIN0H,0x0FFFFFFF); // load the timer by this value

SYSREG_SET(__INTCTL, INTCTL_TMR0RN); //run the timer and i checked that the bit was sit in the assembly code

for(i=0;i<=100;i++)
{

t= __builtin_sysreg_read(__TIMER0H); // the value of t should be derementing each clock cycle(300 MHZ)
printf("t= %d\n",t);
}

return(0);
}

thank you for your time

21469 example code

analog@sgaur.hosted.jivesoftware.com — Mon, 17 Aug 2009 08:53:05 GMT

Is there a reason that all the 21469 example projects are in C ?

I'm porting an assembly project from 21369 to 21469 and can't get the sport initialized properly.

Error when tuning in visual audio

analog@sgaur.hosted.jivesoftware.com — Sat, 29 Aug 2009 16:31:50 GMT

hello
I have meet a problem when using Visual Audio. I follow the instruction to run the executable on my 21369 board, and then enter the tuning mode in VA. But when i double click the modules and try to tune them, an error message turns out to be: Communication error while tuning:Unable to connect to tuning interface or port. I noticed that there is no BTC window in the VisualDSP IDE!!! I cannot find the reason so If any one has some suggestion , please tell me. Thanks~~

Optimized exception handler -- link / unlink

analog@sgaur.hosted.jivesoftware.com — Tue, 13 Oct 2009 13:06:33 GMT

I have an exception handler on the Blackfin which I have allowed the C++ compiler to optimize

Is there any particular reason why this exception, which does not call anything, needs link / unlink instruction present (easiest to see if set to 0.6 version silicon as that does not bring any anonamoly code)?

Is there a pragma I can use to assist the optimizer not insert the link / unlink instruction?

VDK Callback vs. Interrupts

analog@sgaur.hosted.jivesoftware.com — Wed, 17 Jun 2009 15:20:52 GMT

I am trying to figure out the best or most convenient way to generate sine waves using the bf548. I am looking at the audio loopback example that uses the AC97 driver using callbacks. This appears to generate the 48 Khz sample rate that I want, but has a large buffer to fill. Are there any examples of how to use an interrupt to do something similar? I am porting some code from an ADSP-2115, or at least mimic the outputs and it is uses an interrupt with sample by sample manipulation of the output. I will be constantly scanning the frequencies of the output sine waves, and also need to be able to generate single wave outputs with variable pulsewidths reprates and duty cycles.

I am new to the DSP side of the Blackfin, having written mostly interface code, so any advice or examples would be helpful.

Jay Walther

SPI interprocessor communication between two Blackfins

analog@sgaur.hosted.jivesoftware.com — Wed, 07 Oct 2009 13:40:47 GMT

Hi,

is there any available example for communication between two Blackfins via SPI in Master/Slave mode

background is that i want to connect two independent Blackfin Boards an do a cyclic data exchange between this two plattforms

regards chris

What training is available for ADI DSPs

analog@sgaur.hosted.jivesoftware.com — Fri, 16 Jan 2009 23:15:35 GMT

I'm thinking about using an ADI Blackfin Processor and I would like to know what training is available to help me get started with my development?

[Error li1021] The following symbols could not be resolved: ADIMT9V022EntryPoint (or any other off-chip devices)

analog@sgaur.hosted.jivesoftware.com — Fri, 08 May 2009 14:19:17 GMT

When I implemented the MT9v022 Micron Sensor into my code, I've got following linker error;

[Error li1021] The following symbols referenced in processor 'p0' could not be resolved:
'ADIMT9V022EntryPoint [_ADIMT9V022EntryPoint]' referenced from '.\Debug\MyTestProject.doj'

Memory storage on the BF548

analog@sgaur.hosted.jivesoftware.com — Mon, 31 Aug 2009 03:06:08 GMT

Hi guys,

So, we've been working on a word recognition project, and we've got some models that we need to store on the board.

So far, we've simply been storing them in header files, and #included said header files to compile with the project.

However, we keep getting "Hardware error". This (we assume) is due to there being insufficient memory...

How else can we store things like these on the board? We need to store approx 20x of each of these: 13*1 vector, 2*13*13 vector, and that's just the models. We also need to store a 32768 value of an audio input, perform windowing on this input (into segments of 512 long samples), and then perform fft's etc on the data.

So... where can we store these variables to free up precious memory? Preferrably in a location which is fast... (ie: HDD would be slow, so preferrably a ROM or RAM memory).

Any tutorials on how to access said memory and use it in compiler would be appreciated, thanks.

What is the difference between the ADDS and ADZS part numbers?

analog@sgaur.hosted.jivesoftware.com — Mon, 19 Jan 2009 12:37:32 GMT

What is the difference between the ADDS and ADZS part numbers, and which software versions suport them?

BF561 EZ KIT to OEM Module

analog@sgaur.hosted.jivesoftware.com — Sun, 01 Nov 2009 20:10:10 GMT

Hi everybody,

I am using the BF561 EZ KIT as a prototyping tool and am now wondering about

how to create an oem board for an enclosure, etc. While the reference designs

are helpful for creating my own, I was hoping someone will have gone through

the trouble already. What is needed: video in ports, video out ports,

and either an ethernet or rs232 port too. Basically, something pretty similar to

the BF561 EZ Kit.

Does anyone have any suggestions/pointers/experience on who/what has worked

in the past? I will not take it as an explicit endorsement. The collaborative list

on AD's site is quite long and hoped to cut down the search time.

Am I delusional to think this has already been done?

Regardless, thanks for your help.

DFWSwEng

Core Access to an External Port Buffer (EPBx) is Hung

analog@sgaur.hosted.jivesoftware.com — Wed, 16 Sep 2009 10:40:31 GMT

Hi,

I'm using a SHARC 21160 chip, and I'm seeing some kind of interrupt-related problem which *usually* causes the processor to lock up with the error message "Core Access to an External Port Buffer (EPBx) is Hung".

The chip is on a board with an FPGA, and the two communicate using shared memory. (My knowledge is a bit hazy here as I wasn't involved with the board design or the FPGA code.) The function that is causing issues is receiving from a serial UART. The FPGA manages this - when it receives a character, it places it in a certain location in shared memory, then fires an interrupt at the SHARC to let it know that new data has arrived.

On the SHARC, I associate that interrupt with a particular function, i.e. "interrupt(SIG_IRQ0, UARTInterrupt);" where UARTInterrupt is the name of my function. This problem does not occur when the interrupt is ignored (after "interrupt(SIG_IRQ0, SIG_IGN);"), only when it is associated with a function. The problem *does* occur even if UARTInterrupt is empty (i.e. "void UARTInterrupt(void) {}").

It seems to be related to the rate at which the interrupt is called. If I set a serial client on a PC to send one character every 0.2 seconds, I never see the problem. If, however, I hold down a key causing characters to be sent faster, I get this problem within a few seconds. If I paste in a big block of text and send it all at once, the problem happens immediately.

The baud rate is set at 38400b/s, could it be that this causes interrupts to fire too quickly (maybe one's firing before it's finished dealing with UARTInterrupt() from last time - but in which case, why does the problem persist when UARTInterrupt() is empty)? Unfortunately, I have no access to change the baud rate that the FPGA uses.

Is there an interrupt queue, some kind of stack of interrupts-waiting-to-happen that we're overfilling? The fact that the problem does not happen immediately when a key is held down would seem to suggest that something somewhere is filling up. (If there's no such thing in the SHARC, it could of course be in the FPGA.)

To add further confusion, the "Core Access Hung" problem is not the only thing that can happen - sometimes, the chip resets itself instead. This is rarer, happening 5 or so of the two dozen times I've caused this problem to occur.

If anyone has any clue what might be happening here, I'd be very grateful!

Thanks,

Ian Renton

PPI frame sync

analog@sgaur.hosted.jivesoftware.com — Thu, 25 Jun 2009 08:32:59 GMT

In BF, PPI supports both frame sync mode and sync less mode (ITU656).

But to decide which mode is to be used? Is this based on hardware or anyother specificaiton?

example C code for SPI receive

analog@sgaur.hosted.jivesoftware.com — Thu, 16 Jul 2009 17:18:27 GMT

Hello,

I've bought ADZS-21369-EZLITE.

In VisualDSP++ and AD website are 3 examples:

1. SPI Core Driven (C)

2. SPI DMA Driven (C)

3. SPI DMA Chaining (C)

There is only /*Set up loop to transmit data*/

but no for receiving data.

I would like to connect ADSP21369 with ADIS16350 by SPI.

Please help me, show me how it works.

Milos

Malloc specification

analog@sgaur.hosted.jivesoftware.com — Tue, 23 Jun 2009 09:20:04 GMT

1.What time taken for malloc ,considering the worst case .

2.Which Algorithm is been used for Heap allocation (First hit or last hit )

3.Is garbage collection put in practice if so please let me know the condition when this happens

4 What is prerevisits when using it considering the worst case .

5.Can i find the build for Standard library's as if we need to create a custom malloc function call .

This is with regards to Blackfin

BF561 SDRAM interface

analog@sgaur.hosted.jivesoftware.com — Fri, 15 May 2009 09:52:54 GMT

I am using ADSP-BF561 EZ-Kit. I have query of SDRAM interface with
BF-561 processor. MT48LC16M16A2 - 4 Meg x 16 x 4 banks

why BF-561 A18-A19 pin connected to BA0-BA1?

For example, if I am writing data to 0x1000000 SDRAM address, then it
goes to first bank means IA25-24 is 0x01 but what about A18-19?

Can you please explain me this in detail?

Where is the adsp-21362 symbol?

analog@sgaur.hosted.jivesoftware.com — Tue, 30 Jun 2009 08:27:59 GMT

I can find the footprint of adsp-21362 from protel type,but I'm confused when i download ADI_All_Protel99_Symbols that don't have the adsp-213621's name in the folder.

A11 signal when using SDRAM

analog@sgaur.hosted.jivesoftware.com — Thu, 09 Apr 2009 11:28:24 GMT

We have connected address signal A11 from Blackfin processor BF531 (instead of A12) to A11 of the SDRAM. We will implement a workaround in software by reducing usable memory map. But is the behavior of signal A11 predictable when SDRAM is accessed? Will an access to assynchronous memory between two SDRAM accesses misposition the SDRAM access?

Looking for a comparison of the C compiler efficiency/benchmarks and hand coded assembly

analog@sgaur.hosted.jivesoftware.com — Thu, 19 Feb 2009 10:43:06 GMT

Is a comparison of the C compiler efficiency/benchmarks and hand coded assembly available?

External Voltage Regulator and Internal voltage regulator Blackfin

analog@sgaur.hosted.jivesoftware.com — Wed, 08 Jul 2009 07:38:37 GMT

What are things to be taken care of if we are designing a board for which can use either

External or Internal Voltage regulator .

Is a major change need if we have to more from External voltage regulator to Internal voltage regulator.

Please let us know Software and Hardware changes we have to undergo ,as this will be really helpful.

VDK semaphore

analog@sgaur.hosted.jivesoftware.com — Tue, 30 Jun 2009 01:58:21 GMT

i am using custom application, which is having many threads and semaphore.

while in a case, the semaphore is posted from ISR to a thread.

But in the thread, I am not receiving the semaphore.

I thought of checking the state of semaphore by vdk status.

since the application is big, it takes long time to open the window.

Any other way to check the status of the semaphores/threads status??

Problem adding / locating BTC lib files for BF533

analog@sgaur.hosted.jivesoftware.com — Tue, 23 Jun 2009 02:56:58 GMT

Hi,

I would like to add a BTC to a project based on the BF533. I have just migrated up to VDSP5 version 5.0.6.0 (idde 8.0.6.76). My problem is i cannot find the files mentioned in the help topic. This is my first use of BTC.

The help topic states "Browse to the appropriate "lib" folder of your VisualDSP++ installation and select the correct library file." It then gives the following chart

Processor	BTC Library
SHARC ADSP-2126x	libcbtc26x.dlb
SHARC ADSP-2136x	libcbtc36x.dlb
Blackfin	libbtc53x.dlb

I cannot find libbtc53x.dlb or libbtc533.dlb as suggested for Blackin processor even if i do a windows search on whole hard drive or Analog directory.

On closer inspection the directory below does not contain a BF533 folder

C:\Program Files\Analog Devices\VisualDSP 5.0\Blackfin\lib has many variant named folders, and where it appears the BF533 should be in the explorer window, the sub folders jump from bf532_rev_any to bf534_rev_0.0

What point or instruction am i not reading correctly? OR...Is this an installation issue in which i event i must update using the install disc?

Thanks in advance

Jason

Trouble in transferring 16 bit data on BF561 SPORT

analog@sgaur.hosted.jivesoftware.com — Fri, 29 May 2009 09:42:19 GMT

We are using BF533 and BF561 in our project and we noticed that, we cannot transfer data on SPORT which is 16 bits or less? We are using core mode of operation? Any ideas on what went wrong?

Linking Limit

analog@sgaur.hosted.jivesoftware.com — Fri, 04 Sep 2009 21:04:46 GMT

i want t impelement biometrical application using EZ KIT LITE board TigerSHARC. firstly i design the model in SIMULINK. I CONNECT TO THE vISUALDSP++ THROUGH EMBEDDED LINK BETWEEN MATLAN AND VISUALDSP. EVERY THING IS GOING WELL. MY PROBLEM WHEN I want to load an image of size 256x256 pixles into the KIT every thing is stopped and i recieve errors. but when image is small than 100x100 pixel every thing is correct. so that i know there is linking limit. can u help me to solve this problem. do u have any advice.

DAI and DPI support in Simulator for SHARC

analog@sgaur.hosted.jivesoftware.com — Wed, 08 Jul 2009 21:43:48 GMT

Hi Tools,

Can you please let me know if the VisualDsp++ 5.0 Simulator provides support for DAI and DPI pins? Will any of the registers work?

This question came up as a part of the following post,

http://ez.analog.com/message/2369#2369

Please let me know,

Thanks,

Deepa

How do I use your MP3 decoder in my application?

analog@sgaur.hosted.jivesoftware.com — Mon, 31 Aug 2009 16:09:15 GMT

How do I use your MP3 decoder in my application?

How do I generate a production-ready data file for my target system's self-boot EEPROM?

analog@sgaur.hosted.jivesoftware.com — Thu, 23 Jul 2009 20:09:10 GMT

I am using a SigmaDSP with self-boot functionality (such as the ADAU1701, ADAU1702, ADAU1401, ADAU1442, ADAU1445, and ADAU1446).

How do I generate a production-ready data file for my target system's self-boot EEPROM?

Parallel Assembly Instructions for multiply

analog@sgaur.hosted.jivesoftware.com — Wed, 19 Aug 2009 15:33:11 GMT

I need to perform a 32x32 bit multiply on two data buffers within a filter routine for a BF518/12. So, for it to be as efficient as possible, I wrote it in assembly. The code within the primary loop is as follows:

A1 = R2.L * R1.H;
A1 += R2.H * R1.L;
A1 = A1 >>> 16; /* arithmetic right shift */
A1 += R2.H * R1.H;
A0 += A1;

R1 = [I1++];

R2 = [I0++];

Does anyone have any ideas for how I might execute some of these instructions in parallel? I'm still novice at using the blackfin's assembly instructions.

How do I change the sample rate of my SigmaStudio system?

analog@sgaur.hosted.jivesoftware.com — Mon, 12 Oct 2009 15:09:44 GMT

The default sample rate for SigmaStudio projects is 48 kHz. I want to run my system at a different sample rate. How do I do so?

Frequency shift

analog@sgaur.hosted.jivesoftware.com — Sat, 08 Aug 2009 07:45:55 GMT

Hi all,

In my project I must make frequency shift of signal. I wrote program in C, but result is incorect. For example I use article Zoom-FFT Spectrum analyzer. I use this formula for shifting: y(n)=x(n).e^(j.N.fn).

My code is:

// input sin signal

void sinus (void)
{
 int i;
 //generirane na entry signal//
 for(i=0;i<256;i++)
 input[i]=(50* sin(2*Pi*K*i/256));
}

// shifting

void shift(void)
{
int i;
for(i=0;i<256;i++);
input[i]=(expf(fn*i*256))*input[i];
}
This algorithm don't work. Can you help me, I wrote this program for BF532.

Swissranger

analog@sgaur.hosted.jivesoftware.com — Thu, 22 Oct 2009 04:31:07 GMT

Hey,

Has anyone here worked with the Swissranger with a Blackfin? On the Swissranger driver

page they list drivers for the Blackfin - however they are not supporting them anymore.

If anyone has used it or worked with the Swissranger and Blackfin it would be interesting to

see how they went and how to set it up.

Thanks

printf in vdsp 5.0 update 6

analog@sgaur.hosted.jivesoftware.com — Tue, 27 Oct 2009 07:31:43 GMT

I have a program which runs fine using vdsp4.5 but fails when I tried to update to vdsp 5.0.

The problem is that printf generates a kernelpanic, with a kernel status error of kInvalidMutexID.

Is some kind of initialization of vdk needed before I can use printf? any specific services or

drivers that needs to be initialized?

Multi-Application Boot from BF52x NAND

analog@sgaur.hosted.jivesoftware.com — Mon, 05 Oct 2009 22:02:24 GMT

I've having difficulties booting applications located in different blocks of NAND on the BF526 rev 1 silicone.

Is the general approach to call boot rom functions from initcode?

Such as

bfrom_NandBoot( 0x20000, 0 , 0 , NULL ); // app #1

bfrom_NandBoot( 0x40000, 0 , 0 , NULL ); // app #2

or is there a different recommended approach?

My current boot stream is processed and jumps to exception on the bfrom_NandBoot() call.

Thankx

Powering non-used VDDRTC and VDDFLASH when VDDEXT is out of their respective specifications

analog@sgaur.hosted.jivesoftware.com — Fri, 25 Sep 2009 06:16:04 GMT

Hello,

ADSP-BF51x datasheet states on page 23 that when not used VDDRTC and VDDFLASH should be powered from VDDEXT. But what if VDDEXT is out of specifications for those domains? Say VDDEXT is 3.3V while VDDFLASH maximum is 1.9V or 1.8V while VDDRTC minimum is 2.25V?

AdvancedExpertDAI without target?

analog@sgaur.hosted.jivesoftware.com — Thu, 18 Jun 2009 17:36:51 GMT

I was hoping to configure my SRUs without having a target connected, but the expert tool insists that the appropriate target be attached.

Anyone know of a work-around?

ADSP-BF51x MAC Tmdcih parameter

analog@sgaur.hosted.jivesoftware.com — Thu, 01 Oct 2009 02:49:34 GMT

Hello,

ADSP-BF51x datasheet states in the table 42 that parameter Tmdcih=11.5 ns min (MDC Rising Edge to MDIO Input Invalid (Hold)).

But IEEE 802.3 standard states that MDC to MDIO (Read from PHY) delay = 0...300 ns. Delay can be less, than 11.5 ns?

Tell us what you think

analog@sgaur.hosted.jivesoftware.com — Thu, 18 Jun 2009 00:06:31 GMT

We want to hear from you. Use this space to tell us what you think of EngineerZone. What things do you like? What suggestions do you have for improvement? Log-in to post your feedback so we can continue to improve the site to meet your needs.

Thanks!

AndyR

the confliction between Data Cache and async access

analog@sgaur.hosted.jivesoftware.com — Wed, 30 Sep 2009 08:49:54 GMT

My customer used data Cache in BF533, and they found async access will cause"unknown exception" via EBIU. If disable data Cache, such exception will disappear. Had anyone encountered similar problem?

Code example for using twi/i2c with adsp-21369 ?

analog@sgaur.hosted.jivesoftware.com — Tue, 27 Oct 2009 14:43:59 GMT

Hello,

I'm trying to configure a codec (ad1937) thanks to the Two Wire Interface of the adsp-21369, via the I2C protocol.

My code doesn't work at all. I'll feel fine with a little code example using twi/i2c for a master transmit / receive transfer (I didn't find any help on the analog website...)

Thank you for your attention,

mmmathieuuu.

Combining C and ASM and computing mean and std

analog@sgaur.hosted.jivesoftware.com — Sat, 18 Jul 2009 09:28:20 GMT

Hello everybody,

I am trying to write a program for amplitude meter for ADSP-21364.

I modified analog talkthru IN-OUT ASM where I put an easy LED blink method.

in my ISR is:

r10=dm(RXSP0A);

nop;

r1 = 0xd50000;
comp(r1,r10);//r10,r1
if ge jump skipled1; //le, ge
bit tgl FLAGS FLG8;
nop;nop;
skipled1:

So this I use to blink with led when input value r10 reach the value r1.

Now I want to set the r1 value (treshold) automatically,

using mean value (W-Value) and std (standard deviation)

Accordign to manual ADSP-2100 and DSP Guide i decided to

combine C and asm code and using mean & rms signal processing functions

or to rewrite:

100 CALCULATION OF THE MEAN AND STANDARD DEVIATION

110 '

120 DIM X[511] 'The signal is held in X[0] to X[511]

130 N% = 512 'N% is the number of points in the signal

140 '

150 GOSUB XXXX 'Mythical subroutine that loads the signal into X[ ]

160 '

170 MEAN = 0 'Find the mean via Eq. 2-1

180 FOR I% = 0 TO N%-1

190 MEAN = MEAN + X[I%]

200 NEXT I%

210 MEAN = MEAN/N%

220 '

230 VARIANCE = 0 'Find the standard deviation via Eq. 2-2

240 FOR I% = 0 TO N%-1

250 VARIANCE = VARIANCE + ( X[I%] - MEAN )^2

260 NEXT I%

270 VARIANCE = VARIANCE/(N%-1)

280 SD = SQR(VARIANCE)

290 '

300 PRINT MEAN SD 'Print the calculated mean and standard deviation

310 '

320 END

from DSP Guide - chapter 2

But I now I don´t know if I can combine c and asm (in C i can use mean & rms functions)

and both how to rewrite code above for asm.

Can anyone help me telling which of two ways will be more efficent?

If anyone has these things rewrited and functional for asm and can post them

it will be great.

Thank for your help.

Kind regards,

Martin S. (roland)

voice recognition with ADSP 21369 sharc

analog@sgaur.hosted.jivesoftware.com — Mon, 12 Oct 2009 09:17:13 GMT

This thread would be better placed in the VisualDSP++ Development Tools category, and has been moved here:voice recognition with ADSP 21369 sharc

Thank you.

External frame sync(SPORT) pulled from the 3.3V logic voltage down to 1.7V

analog@sgaur.hosted.jivesoftware.com — Wed, 19 Aug 2009 10:34:47 GMT

ADS-BF 518 EZ-Board (ADSP-BF518 KSWZ-EN6)

I multiplex the SPORT1 in the P4 of the Board, and when I connect

the TIMER0 (also multiplexed in P3 of the Board, other TIMERs the

same situation)out as a external frame sync signal to SPORT1(pin20 of

P4), the original 3.3V voltage is pulled down to less than 1V(only about

1.7V), then the SPORT interface can't capture the frame sync signal, so

how can I keep the 3.3V voltage?

Are there anyone here who came across the same problem? I’ll really

appreciate that if anyone can help me out, thanks!

Please Don't Post Job Opportunities [Looking to Hire Ultra High Speed Communication DSP expert]

analog@sgaur.hosted.jivesoftware.com — Fri, 03 Jul 2009 20:48:21 GMT

A fully funded startup in Boston are is looking to hire a ultra high speed communication DSP expet. The candidate will be a member of a small multi-disciplinary team working on the next generation coherent optical communications products. If you have leads please contact me at
**email address removed by moderator**

Message was edited by: AndyR - Changed subject and removed email address from posting.

Can I copy the EZ-Kit lite hardware design?

analog@sgaur.hosted.jivesoftware.com — Tue, 05 May 2009 20:58:20 GMT

Can I copy the EZ-Kit lite hardware design?

What is the cost if I want to release your decoder in my product?

analog@sgaur.hosted.jivesoftware.com — Mon, 31 Aug 2009 16:28:25 GMT

What is the cost if I want to release your decoder in my product?

delay program for ADSP-TS201

analog@sgaur.hosted.jivesoftware.com — Wed, 22 Jul 2009 13:37:33 GMT

what is the best method to make a delay program with c language for ADSP-TS201 for a certain period of time (ex: 1usec)

LwIP loopback

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Apr 2009 12:10:05 GMT

How can I do the loopback of LwIP Client <-> Server in the same Kit?

Loading code to 21371 using 32-bit SDRAM is extremely slow

analog@sgaur.hosted.jivesoftware.com — Fri, 08 May 2009 13:51:10 GMT

When loading my executable to my 21371 target, the SDRAM sections take an excessive amount of time to load, even when there is not a lot of data

SigmaStudio example files

analog@sgaur.hosted.jivesoftware.com — Thu, 06 Aug 2009 16:00:08 GMT

Are there any example projects available for SigmaStudio? Where can I get these?

ADSP-21369 EZ-Kit Lite Board stack-up

analog@sgaur.hosted.jivesoftware.com — Mon, 13 Jul 2009 10:34:48 GMT

Hi,

Where can I find information on the board stack-up of the ADSP-21369 EZ-Kit Lite board?

What is the distance between the layers? How much copper is used on each layer? What type of laminate/pre preg is used?

Best regards

Peter Karlsen

Problem with Fract16 data type in FFT.

analog@sgaur.hosted.jivesoftware.com — Tue, 01 Sep 2009 06:35:02 GMT

Hi, all

I made FFT function, for input signal I use sinus function from type float. But I can't convert float to fract16. Are there FFT function without fract16? What I must make, for FFT.

This is my code:

void rfft_fr16_example (void)
{
int i;
//entry signal//
for(i=0;i<FFT_size;i++)
input[i]=50*sin_fr16(2*Pi*K*i/256);

//Twiddle table//
twidfftrad2_fr16(twiddle, FFT_size);
//calculation FFT//
rfft_fr16 (input, out, twiddle, 1,FFT_size, &blk_exp, 1);
for(i=0;i<FFT_size;i++)
{
R[i]=(sqrt(out[i].re*out[i].re + out[i].im*out[i].im));

}
}

Thanks, Yanko

Booting from Atmel D-type devices

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Apr 2009 11:34:33 GMT

I am trying to boot a BF533 processor using Atmel SPI Flash, AT45DB081D. I am able to program the AT45DB081D device and do a read operation to verify whatever I have written.

But I am not able to boot the processor using this memory device. Can you tell me how I can debug this?

ADXL345 and 16-bit PIC interfacing

analog@sgaur.hosted.jivesoftware.com — Sun, 04 Oct 2009 16:36:12 GMT

I am designing a device that uses three ADXL345 and a 16-bit PIC microprocessor to implement a mouse. One accelerometer on the palm, to move the mouse cursor along the x and y-axis, and the last two accelerometers on the pointer and middle finger, to incorporate tap and double tap. I would like to use I2C protocol to interface the sensors and a PIC24F16KA102, but I do not have much experience with this at all. I have looked all over the internet but cannot seem to find a great resource. Does anyone know of any example code that would, for example, perform a read from the accelerometer; just to get me started. Any help is appreciated! Thank you.

Custom Board Support XML file settings do not initialize SDRAM correctly

analog@sgaur.hosted.jivesoftware.com — Mon, 11 May 2009 09:31:56 GMT

I have created an Custom Board Support XML file for my target. The values used for the EBIU registers are based on values set in a working project so I know the all of setting in this XML should be OK. However, when I use this XML I am encountering issues accessing SDRAM. The values I am using are as follows:
EBIU_SDRRC=0x026B
EBIU_SDBCTL=0x25
EBIU_SDGCTL=0x80111109

drivers USB CDC (COM port)

analog@sgaur.hosted.jivesoftware.com — Mon, 22 Jun 2009 17:22:08 GMT

Where can I find free USB drivers (CDC for COM port) for BF54x ?

Blackfin 537 32 bit math

analog@sgaur.hosted.jivesoftware.com — Thu, 30 Jul 2009 12:52:51 GMT

HI,

The blackfin 537 is an optimised architecture for 16 bit fixed point math. However i am forced in a situation where i have to deal with 32 bit samples.

Does anyone of you have 32 bit fixed point routines for basic operations like addition, multiplication , division at high precision(more than 40 bits)?

It will be helpful if you could give some pointers on this.

-geek

Failed to run Landscape LCD EZ-Extender Examples on BF526

analog@sgaur.hosted.jivesoftware.com — Wed, 19 Aug 2009 07:53:19 GMT

I am working on BF526 with LCD support.

1. Platform is VDSP5.0 Update 6, BF526-EZKIT-LITE(Rev 0.2), Landscape LCD EZ-Extender (Rev1.1).

2. Run example code under C:\Program Files\Analog Devices\VisualDSP 5.0\Blackfin\Examples\Landscape LCD EZ-EXTENDER\LCD_ColorBarDisplay\ADSP-BF526, did not work.

3. It was said that a updated code located in ftp://ftp.analog.com/pub/tools/patches/../TAR37970_hotfix.zip, but no such file in server at all.

Please extend your support to help me out, thanks.

robin

FFT Sample Code

analog@sgaur.hosted.jivesoftware.com — Fri, 23 Oct 2009 22:00:19 GMT

Application note EE-263 presents an optimized algorithm for a 256 point 16 bit FFT. It mentions that code has also been developed for a 4096 point FFT. Does anyone know where I can get sample code for the 4096 point FFT?

Thanks.

interfacing blackfin to blackfin processors via uart to uart communication

analog@sgaur.hosted.jivesoftware.com — Mon, 21 Sep 2009 14:38:56 GMT

Hello

I have a question on interfacing uart to uart issue:

I have my own BF533 based boards and I want to communicate between them via UART port.

How do I do that?

Will it suppose to work with connecting 3 wire cable? (RX to TX,TX to RX, GND to GND).

I have tried that and I get no data in my receive board.

I have configured the dma6 for receiving trough uart and dma7 for transmitting trough uart.

If I send data trough other device to the blackfin the data is received OK but from blackfin to blackfin, I get no data even no start of data.

Any ideas?

Thanks in advance

Tzvika

Session Wizard -- two processors on TS201 board

analog@sgaur.hosted.jivesoftware.com — Tue, 15 Sep 2009 23:04:12 GMT

Hi there

Back again teaching the TigerSHARC to a graduate class. Had the same problem I always have at the start of term -- course gets taught 2 years out of 3, so I have not touched the board for 18 months.

You start VDSP, go to "New session", use TS201 "Add new session" -- add TS201S session, emulator and then go to finish -- VDSP complains that it is seeing 2 processors in JTAG line and not 1 that it expects.

AFter a couple of attempts I remember the fix from 2 years ago -- go to configurator and select a two processor TigerSHARC session, copy and test that to check board is not blown. Now activate new session in VDSP and the Session wizard sees the new 2 procesor session

Question is -- why does the selection wizard not offer a 2 processor session initially?

Printf execution doesn't complete when using a while loop

analog@sgaur.hosted.jivesoftware.com — Wed, 03 Jun 2009 11:20:13 GMT

My code fails to print anything to the VisualDSP++ console when my printf is followed by a while(1) loop. When I remove the While loop the printf outputs as expected.

Can someone explain this behaviour?

Bypass capacitor placement for ADSP-21362/3 for LE_QFP package

analog@sgaur.hosted.jivesoftware.com — Wed, 15 Apr 2009 15:49:39 GMT

Can you please confirm the proposed placement of bypass capacitors for ADSP-21362/3 for LE_QFP package?

SRU/FLAG Macros for 2136x?

analog@sgaur.hosted.jivesoftware.com — Wed, 24 Jun 2009 17:58:49 GMT

I know I'm just being lazy, but does anyone have macros or routines to set and clear FLAGS or PINS from C?

For example: if I have FLAG5 tied to DPI_PIN9, which controls the GRN_LED, I'd like to have a function that sets or clears the LED:

setPIN (GRN_LED); // set FLAG5 HI

clrPIN (RED_LED); // set FLAG6 LO

Or should I bypass using the FLAGs, as they can only be reached from assembler?

Suggestions?

Thanks

code example I2S

analog@sgaur.hosted.jivesoftware.com — Mon, 22 Jun 2009 17:30:02 GMT

Have you some code examples to run a I2S connection (SPORT) with BF548 ?

Speed of two core DSP's

analog@sgaur.hosted.jivesoftware.com — Thu, 06 Aug 2009 09:42:20 GMT

Hello!

Whether there will be two core DSP's in the near future with clock greater than 600MHz?

Thank you

ADSP 21062 - External Port Buffer (EPBx) is hung at PC

analog@sgaur.hosted.jivesoftware.com — Tue, 25 Aug 2009 18:48:18 GMT

Hi All In a board we are using 6 ADSP 21062 sharc processors in Multi processing environment The batch code of the processor is ADSP-21062 - cs-160 - EDC2372D-3.0 - 0045 . Flash is connected to the sharc bus along with sram, ethernet and an FPGA.. I can erase the Flash and I could read the contents of the Flash. But, while programming the flash It hangs and gives a message in vdsp as "Core access to an External Port Buffer (EPBx) is hung at PC:0x0201f2" I have attached the screen shot of the message in VDSP 5.0 I have attached the screen shot of the message I get in VDSP The same Flash code is working fine with the same architecture board with ADSP 21062 Processor batch code 0926 and 0849. Help me to resolve this issue in the processor batch with ADSP 21062 Processor batch code 0045. Thanks Mahendravarman

BF518 pin descriptions for LQFP package

analog@sgaur.hosted.jivesoftware.com — Wed, 21 Oct 2009 03:38:12 GMT

In the datasheet:

pin 117 - GND;

pin 127 - NC.

In the ADSP-BF518F EZ-Board:

pin 117 (TEST) is connected to GND through a jumper;

pin 127 is connected to test point.

What purpose of these pins?

Why can't I access private OTP in Secure Mode?

analog@sgaur.hosted.jivesoftware.com — Sun, 19 Apr 2009 13:44:18 GMT

I wrote an application that makes use of Lockbox and that attempts to write some secrets into the private area of OTP memory.

However, even when I enter Secure Mode, I get an error when accessing private OTP memory.

Shouldn't I be able to access private OTP memroy when the processor is in Secure Mode?

BTC plot Error when using XYplot.

analog@sgaur.hosted.jivesoftware.com — Mon, 31 Aug 2009 16:52:10 GMT

Hi,

I am using an BF533 ezkit lite with the debug agent. I have plotted some data using some defined channels and they plot on a Line Plot but using the same channels in a new XY plot the IDE complains that the channels specified are not valid memory. This is confusing since the same channels plotted in the Line Plot.

Thanks for any ideas or suggestions.

Scot R

Standalone Debug Agent

analog@sgaur.hosted.jivesoftware.com — Tue, 21 Jul 2009 22:37:46 GMT

Will the Standalone Debug Agent - ADZS-DBGAGENT-BRD - work with my custom BF561 board that was designed with the ADI standard JTAG connector? Currently my custom board works great with the HP-PCI JTAG emulator. Is the ADZS-DBGAGENT-BRD available for purchase to be sold with my custom board as needed?

Thanks

Rick

We are planning to move the floating license server to new PC. How we can do this? Is there any recommended way?

analog@sgaur.hosted.jivesoftware.com — Wed, 04 Mar 2009 14:50:09 GMT

We are planning to move the floating license server to new PC. How we can do this? Is there any recommended way?

Driver Files on EZ-Kit 21469

analog@sgaur.hosted.jivesoftware.com — Thu, 06 Aug 2009 09:03:46 GMT

Hi Guys,

We are looking for the flash drivers on the EZ-Kit 21469, it seems those are not included in VDSP 5.0 update 6? Please send us the driver file if those are avilable at this time.

Best regards,

Kishore.

Can I use the examples from the multimedia starter kit in my development?

analog@sgaur.hosted.jivesoftware.com — Mon, 31 Aug 2009 16:37:51 GMT

Can I use the examples from the multimedia starter kit in my development?

Can I simultaneously input both analog and digital signals to a SigmaDSP?

analog@sgaur.hosted.jivesoftware.com — Thu, 23 Jul 2009 18:43:12 GMT

I have both analog and digital (I2S) signals in my design and want to process them both in a SigmaDSP. Can I mix and process these together, or can the SigmaDSP only take an input from one at a time?

How do you use the TMREXP pin?

analog@sgaur.hosted.jivesoftware.com — Fri, 19 Jun 2009 13:39:56 GMT

I couldn't find any examples or descriptions of how to use the TIMEXP pin that is shared with FLAG3.

My Maxim MAX3100 RS232 driver needs a a 50% duty-cycle, 3.68MHz clock.

When I laid out my PCB, I thought I would be able to generate it with one of the timers, and output it though TIMEXP to keep from using that last precious DAI pin.

When I read through the documentation, I couldn't find any way to do this. With the lack of any information to the contrary, I reached the conclusion that the TIMEXP pin is tied solely to the core timer, and that it only produces a single clock-time pulse every time the core-timer expires. I couldn't find any sections in the manuals that described how to use the core timer, but our project uses VDK, and I bet VDK uses the core timer for it's scheduler, so I don't think it's available for me to use.

These are all just guesses. Can you give me information on the use of the TIMEXP pin, and the core-timer? Is it really dedicated to VDK? Can I use the TIMEXP pin the way I want, or do I really have to use up my only spare DAI pin?

Thanks,

Bob

Problem with printf() on ADSP-21375

analog@sgaur.hosted.jivesoftware.com — Mon, 27 Jul 2009 16:45:10 GMT

Hello,

I am trying to test an audio application on the EZ-kit lite board.

I am starting from the example "block based talkthru (c)" and I need to monitor the execution time in release mode.

When I call the function printf(), I get this error:

Error verifying user opcode for breakpoint remove at address: 0x210341.

Then I have to delete the session and create a new one to use printf() again, even with other projects.

I think there is a conflict with the SPI...

Any idea to solve this issue?

Thanks,

David

Blackfin interrupt vectors

analog@sgaur.hosted.jivesoftware.com — Tue, 20 Jan 2009 19:06:36 GMT

Are interrupts auto-vectored, or does software search for the interrupting source?

CCLK and SCLK to minimum value

analog@sgaur.hosted.jivesoftware.com — Tue, 19 May 2009 15:26:27 GMT

I'm trying to set CCLK and SCLK to its minimum value. But the emulator hangs when I run the code. What should I do?

21363 : 4 I2S In, 4 I2S Out Example

analog@sgaur.hosted.jivesoftware.com — Tue, 01 Sep 2009 14:59:00 GMT

Hello,

I'm using a 21363. I'm looking for an example in C for handling 4 I2S inputs and 4 I2S outputs via the SPORTs. I'm using Visual Audio for the development of the system in between. The I2S I/O signals are all coming and going to the same source (FPGA) so I am using one common I2S Bit Clock and one common I2S Frame Sync for all SPORTs (Rx and Tx).

I looked through several EZ Kit examples but they do not handle this type of I/O. I started by adapting the EZ Kit 21364 SPDIF In/Out code (I stripped all the ADC and DAC code) but I don't know how to handle 4 synchronized inputs using double-buffering and DMA. Since there are 6 SPORTs and my system has 8 I2S signals, I use SPORTs 0 and 1 for the 4 I2S inputs with Rx A and Rx B in each SPORT and I use SPORTs 2 and 3 for the 4 I2S outputs with Tx A and Tx B in each. Since there is only 1 interrupt per SPORT, I looking for the best way to handle the Rx and Tx DMA interrupts for all these signals.

Do you have example code for this?

Thanks in advance.

Steph

kBlockInInvalidRegion - What is the Value Information

analog@sgaur.hosted.jivesoftware.com — Fri, 09 Oct 2009 10:31:33 GMT

This thread would be better placed in the VisualDSP++ Development Tools category, and has been moved here:kBlockInInvalidRegion - What is the Value Information

Thank you.

Looking for memory type/size and procedure for erasing it on the ADZS-HPUSB-ICE

analog@sgaur.hosted.jivesoftware.com — Mon, 27 Jul 2009 14:04:12 GMT

Hi,

Due to corporate security requirements we have been asked to determine the following information about the ADZS-HPUSB-ICE:

1. List of the type and size of memory inside the emulator?

2. A general description on what is stored in data and instruction memory?
3. Is the memory user accessible?
4. What the memory clearance or sanitization procedure is. For example, if the emulator uses volatile memory a power down should be enough to clear the memory. If, however, the memory is non-volatile is there a sanitization procedure?

Can't compile with floating license when not "administrator"

analog@sgaur.hosted.jivesoftware.com — Thu, 04 Jun 2009 14:02:00 GMT

I run a laboratory with 32 Blackfin stations at the University of Calgary. These stations all access floating licenses over the network. These stations are not in my research labaoratory so I am just a "user" and not an adminsitrator on each system -- ditto for all the 60 students in my class.

The issue is, I can't use VDSP on these stations, it just doesnot work. What can I do to fix the problem.

SS/DD - Using adi_spi as stackable driver on other devices

analog@sgaur.hosted.jivesoftware.com — Wed, 24 Jun 2009 15:23:00 GMT

Hello,

Im using System service/ Device driver for my proj(using BF526). I have two peripherals accessed via spi. Let say one is a codec(say on SSEL5) and another one is an ADC(on SSEL6). I want to create my own device driver for these device using the same architecture as ADI.

But the problem starts by adi_pdd_open() for each of the above mentioned devices . Since these devices need to have an exclusive access to SPI but BF526 has only one physical SPI, so while opening the codec driver and ADC driver how can I stack the spi driver into them? In the adi_pdd_open() for each device should I open the SPI with the same device number namely "0", since BF526 has only one physical SPI. Or how should this be handled ?

Any inputs on this front would be of great help.

Regards

velsen

Question about Loops in Interrupt Handler on ADSP-213xx

analog@sgaur.hosted.jivesoftware.com — Thu, 30 Jul 2009 08:11:10 GMT

Hello all,

I have some concern about a note found in the help of VDSP5.0.

In "Interrupt Dispatchers", about interruptcb() function: "Note: Due to Hardware restrictions on 213xx processors, the loop counter stack can not be saved and restored by the dispatcher"

My understanding of this restriction is that it is not safe to use loops in an interrupt handler because you never know if you will not screw up the loop counter of a lower priority code.

But on the other hand, in the Frameworks provided with VisualAudio (be it Basic or AVR), I can see that the whole rendering/post-processing (which use quite a lot of loops) is completely done in a Interrupt Handler...

My question is: Is it safe to proceed like this?

Sorry, if I missed something here.. I'm new to the SHARC DSPs...

Thanks in advance for your support,

Regards,

Fabian

-------

PS: Using ADSP21375 EZ-Kit Lite 1.0 and VisualDSP++5.0 Update 5 (5.0.5.0),

Blackfin core functionality during PLL transitions

analog@sgaur.hosted.jivesoftware.com — Tue, 20 Jan 2009 19:15:23 GMT

Does the core stall while the PLL transitions to a new frequency setting?

LWIP DHCP Timeout

analog@sgaur.hosted.jivesoftware.com — Wed, 26 Aug 2009 13:24:37 GMT

I have an application running on a Blackfin BF537 that uses VDK and LWIP with DHCP enable.

Is there a way to change the DHCP timeout when looking for an IP address during DHCP discovery?

SPORT interface registers

analog@sgaur.hosted.jivesoftware.com — Tue, 18 Aug 2009 16:23:23 GMT

HI ADI Support,

I am using an audio codec on SPORT1 of BF561 EZ-Kit. The audio codec generates the FSYNC and the Bitclock for the SPORT. The codec generates a 8 kHz FSync and 16 Bit data word per sample but the BitClock is 256 kHz instead of 128 kHz. So the first 16 Bit have the sample data of the audio channel followed by 16 Bit which are not used until the FSYNC occurs. See screenshot in attachment. So actually there are 32 Bits/Clocks between FSYNC but only the first 16 Bits have the audio payload content.

My Sport RCR1 is set to 0x0401

and Sport RCR2 register is set to 0xf which means 16Bit.

Actually between the FSYNC there are 32 Bit. So one option would be to set the RCR2 serial word length to 0x1f. This could be one solution.

I would like to use later the uLaw Compand option which requires 16 Bit data.

My question is now what would be the best settings for Sport RCR1 and Sport RCR2 in order that the second 16Bits are ignored.

Thanks

Thomas

Can I use BF537 Ethernet driver with a PHY other than LAN83C185?

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Apr 2009 20:07:32 GMT

Hi,

The BF537 Ethernet driver provided by VisualDSP is for the PHY(SMSC LAN83C185) on the EZKIT. Can I use it for another PHY?

Does the Blackfin DMA perform fly-by transfers?

analog@sgaur.hosted.jivesoftware.com — Tue, 20 Jan 2009 18:55:09 GMT

Does the Blackfin DMA perform fly-by transfers?

delay program for ADSP-TS201

analog@sgaur.hosted.jivesoftware.com — Wed, 22 Jul 2009 16:11:47 GMT

This thread is not in the correct category and has been moved. You may find ongoing discussion concerning this subject in the Other ADI DSPs category, here:delay program for ADSP-TS201

Thank you, ADI DSP Forum Admin.

Starting lab with SHARC

analog@sgaur.hosted.jivesoftware.com — Mon, 14 Sep 2009 15:55:41 GMT

Hello,

In our School we have several ADSP-21065L EZ-LAB and a DSP++ software.

I am a bit newer with this devices and i'm trying to develop a students labs to work.

I started to run a EZ-Kits examples which one of them is not working "Talk-Through demo".

My intention with this post is to ask help to the forum about this trouble.

Nevertheless, i would like to seek the c programs (in signal processing like FIR and IIR) that could be study, changed and implemented by our students.

Thaks in advance,

Mário Assunção

Problems to use data from instruction RAM

analog@sgaur.hosted.jivesoftware.com — Fri, 09 Oct 2009 09:48:39 GMT

Hi,

I have a large table with const data.

Because I want to save data RAM I want to put this table into the instruction RAM.

In one of my calculating functions I use the following assembler line:

R1 = [I2++M2] ;

(remember I2 points to instruction RAM)

After that instruction i got ( "Unknown excception").

Somewhere I red that it ist not allowed to use DAG register in instruction RAM.

Does anybody know how to use data (efficient like DAG) from instruction RAM.?

regards

amok

BF51x Peripheral Mux of SPI1 & SPORT1

analog@sgaur.hosted.jivesoftware.com — Fri, 19 Jun 2009 14:57:51 GMT

I would like to use both the SPORT1 and the SPI1 on the BF512, but am not sure if this will cause contention as some of the I/Os are muxed to the same chip pins. According the hardware reference manual, the SPORT1 and SPI1 I/O are muxed through port H on the chip:

	1st Function	2nd Function
PORTH_MUX	00	01
BIT[1:0]	DR1PRI RFS1 RSCLK1 DT1PRI	SPI1 SS SPI1 MISO SPI1 SCK SPI MOSI
BIT[3:2]	TFS1 TSCLK1	AOE ARDY
BIT[5:4]	DT1SEC	UART1 TX
BIT[7:6]	DR1SEC	UART1 RX

If I select the SPI1 interface using BIT[1:0], can I still use the SPORT 1 Rx/Tx by selecting the DT1SEC & DR1SEC with BIT[7:4]? Now, if I use DT1SEC, DR1SEC, I still need to set the SCLK and frame sync rates in the SPORT1 configuration registers. I will be generating this timing in the BF512, so I don't need the signals actually to chip outputs. If I try to do this, will the SPI1 signals cause any contention with the SPORT1 operation or vice versa? Any thoughts?

What is the operating temperature range of ADI Emulators?

analog@sgaur.hosted.jivesoftware.com — Wed, 18 Feb 2009 09:28:54 GMT

What is the operating temperature range of ADI Emulators?

Blackfin SPORT 8 bit communication without DMA

analog@sgaur.hosted.jivesoftware.com — Tue, 18 Aug 2009 12:28:52 GMT

Hi,All,

I'm designing BF548+BF534 structure, and use SPORT for intra communication between BF548 and BF534. Both have the same SCLK and SPORT CLK value. And transmitter use internal Frame Sync and Clock signal,while receiver use external Frame Sync and Clock signal.

I just use code like:

while ((*pSPORT1_STAT & RXNE)==0);
return *pSPORT1_RX;

to transmit and receive data.

I found that if I set SPORTs as

*pSPORT1_TCR2 = 16; //or any 16<=length<=31
*pSPORT1_TFSDIV = 31;

........................

*pSPORT1_RCR2 = 16; //or any 16<=length<=31
*pSPORT1_RFSDIV = 31;

There's correct Frame Sync, Clock and data.

If I set SPORTs as

*pSPORT1_TCR2 = 15; //or any 2<=length<=15
*pSPORT1_TFSDIV = 31;

........................

*pSPORT1_RCR2 = 15; //or any 2<=length<=15
*pSPORT1_RFSDIV = 31;

*pSPORT1_TCR2 = 7;
*pSPORT1_TFSDIV = 7;

........................

*pSPORT1_RCR2 = 7;
*pSPORT1_RFSDIV =7;

There's no Frame Sync, and no data transmitted, but there's correct clock signal.

Actually I need 8 bit SPORT communication without DMA.

According to <ADSP-BF537 Blackfin Processor Hardware Reference>, P12-22, "setting SLEN to 7 does not produce a frame sync pulse on each byte
transmitted." What does it mean?

Thanks.

about visualDSP++ simulator speed

analog@sgaur.hosted.jivesoftware.com — Thu, 27 Aug 2009 07:25:16 GMT

I run the same program using Microsoft Visual C and VisualDSP++4.5 simulator. the VC spend 2 seconds, but the VisualDSP++4.5 cost 10 hours. how to improve the VisualDSP++ simulator`s speed?

Blackfin DMA vs Cache

analog@sgaur.hosted.jivesoftware.com — Tue, 20 Jan 2009 18:57:25 GMT

When does it make sense to use DMA and when does it make sense to use cache?

SPI Master booting with ADSP-21369

analog@sgaur.hosted.jivesoftware.com — Tue, 08 Sep 2009 09:26:26 GMT

Hello everybody,

I'm currently implementing an ADSP-21369 and I was thinking about the booting scheme. I have a SPI Flash ROM connected to a FPGA (SPI host) and this FPGA is connected to the SHARC DSP. I'd like to use the SPI master booting mode (DSP is master). To sum-up SPI Flash PROM will be remotly programmed via the FPGA. When a boot will happen, FPGA will read the SPI flash and send the boot data to DSP. My question is so:

- When a power-up occurs the FPGA will boot and might not be ready before the DSP. Is the DSP will initiate the booting SPI communication after a power-up (electrical cycle) or after a reset coming from the FPGA?

Sorry if this question seems to be a bit trivial. But I'm a complete newbie in DSP's....

Thanks in advance for your reply.

Cheers,

Jose

Do you have an implementation of AES for Blackfin?

analog@sgaur.hosted.jivesoftware.com — Sat, 18 Apr 2009 00:32:56 GMT

I want to implement encryption on Blackfin.

Do you have an implementation of the Advanced Encryption Standard (AES) for Blackfin?

PLL and SDRAM init for debug large app.

analog@sgaur.hosted.jivesoftware.com — Mon, 13 Jul 2009 18:20:14 GMT

I'm getting stuck with PLL and SDRAM init for debugging. I've coded XML that inits the SDRAM and implemented PLL init in main(); However -- when PLL is being initialized SDRAM content gets lost. My application is too large to fit into L1 code. I'm using HPUSB ICE as emulator. Is there any way to init both PLL and SDRAM to necessary values before app is loaded to SDRAM? Is there a way to debug such application at all?

DB/DTS module in VisualAudio

analog@sgaur.hosted.jivesoftware.com — Wed, 26 Aug 2009 22:40:00 GMT

Hi all,

Do we have DB/DTS decoder(module) in VisualAudio? How can a customer get/use these modules if YES?

Many audio customers in China think VisualAudio is a good tools for audio product design.

Thanks!

Where to find Solder profiles?

lou.leen@silica.com — Thu, 17 Sep 2009 08:09:40 GMT

Hi, where can I find generic solder profiles for particular packages?

I am specifically looking for the characteristics of the 297 ball PBGA package used for the ADSP-BF561SBBZ600.

I expected to find this info in the quality section of the ADI site, but it doesn't seem to be so easy to find.....

Thanks,

Lou

example C code for interrupt from DPI pin

analog@sgaur.hosted.jivesoftware.com — Wed, 05 Aug 2009 15:21:35 GMT

Hello,

Does somebody have any example to generate output on the one DPI pin (by flags or misc - I don't know which is better or where is difference.)

and on the other DPI pin (as a input) generate interrupt?

I tried but it doesn't work.

Can you check it?

Please help me.

Regards,

Milos

#include <def21369.h>
#include <cdef21369.h>
#include <signal.h>
#include <sysreg.h>
#include <sru.h>

void IRQ_Isr(int sig);

int i, j, k=0;

int main( void )
{
// Code for connecting as a input (for interrupt): FLAG4 to DPI_PIN07

SRU (HIGH, DPI_PBEN07_I);
SRU (FLAG4_O, DPI_PB07_I);

// Code for connecting as a input (for interrupt): DPI_PIN8 to MISCB1

SRU (DPI_PB08_O, MISCB1_I);
SRU (LOW, DPI_PB08_I);
SRU (LOW, DPI_PBEN08_I);

//settings for interrupt

(*pDPI_IRPTL) = (EXT_MISC_1_INT ); //unmask individual interrupts
(*pDPI_IRPTL_RE) = (EXT_MISC_1_INT); //make sure interrupts latch on the rising edge

//Set up interrupt priorities
sysreg_bit_set(sysreg_IMASK, DPII); //make DPI interrupts high priority

sysreg_bit_set(sysreg_MODE1, IRPTEN ); // Global Interrupt Enable. Enables (if set, = 1) or disables (if cleared, = 0) all maskable interrupts.

interrupt(SIG_P14,IRQ_Isr);

//end settings for interrupt

// settings for FLAG4
sysreg_bit_set(sysreg_FLAGS, (FLG4O) ); //Setting flag pins as outputs
sysreg_bit_clr(sysreg_FLAGS, (FLG4) ); //Clearing flag pins

// end settings for FLAG4

for(i=0;i<10;i++)

{
sysreg_bit_clr(sysreg_FLAGS, FLG4); //output is LOW

for(j=0;j<10000000;i++)

{ asm("nop;"); } //waiting

sysreg_bit_tgl(sysreg_FLAGS, FLG4); //output is HIGH to generate interrupt

}

void IRQ_Isr(int sig)

{

k++;

}

How to use License Borrowing feature of VisualDSP++

analog@sgaur.hosted.jivesoftware.com — Thu, 07 May 2009 15:26:02 GMT

I am looking for detailed instructions for using new License Borrowing feature in VisualDSP++ 5.0.

Sport problem when simulating Uart TX

analog@sgaur.hosted.jivesoftware.com — Tue, 29 Sep 2009 13:54:39 GMT

Hi,

I need more than one UART in my project (with BF533), so i have to use sport as secundary uart. The communication is between ezkit and a PC. I am using 9600bps 8N1. By now i am using sport register mode (no dma).The reception is working fine, but when i have to transmit some chars the last one is never transmitted right (i get a 0xFF instead). The code below should transmit char 2 and 3. But only char 2 is received by the PC. If i program to transmit three chars, PC only gets two and so on..

regards,

Fagner

My code:

main(){

...

*pSPORT1_TCR1 = 0x0000; // be sure rx port is disabled

*pSPORT1_TCR2 = 0x0000; // be sure rx port is disabled

    // TX config
    *pSPORT1_TCLKDIV = 0x182B;        //118.800.000/2*9600
    *pSPORT1_TFSDIV = 10;            //
    *pSPORT1_TCR2 = 9;
    *pSPORT1_TCR1 = ITCLK | TLSBIT | LATFS| TFSR| LTFS;
    ssync();

     *pSPORT1_TX16 = (unsigned short)0x0264;     //start bit + ch'2' + stop bit
     ssync();
    *pSPORT1_TX16 = (unsigned short)0x0266;     ////start bit + ch'3' + stop bit
    ssync();

*pSPORT1_TCR1 |= TSPEN; //tx enable

ssync();

...

}

void Init_Interrupts(void)
{

    // configure interrupt
    *pSIC_IAR0 = *pSIC_IAR0 & 0xffffffff | 0x00000000;    // map SPORT0 Error Interrupt -> IVG7
    *pSIC_IAR1 = *pSIC_IAR1 & 0xffffffff | 0x33322221;    //

    register_handler(ik_ivg7, SPORT1_ERROR_ISR);
    register_handler(ik_ivg9, SPORT1_ISR);

    *pSIC_IMASK=SPORT1_ERR_IRQ | DMA4_IRQ;
    ssync();

}//end Init_Interrupts

EX_INTERRUPT_HANDLER(SPORT1_ISR) // <--|declaration in exception.h -->
{
 int i;
 unsigned short statreg=0;

 *pDMA4_IRQ_STATUS = 0x1;
 ssync();

while ((*pSPORT1_STAT & 0x0040) == 0) // While HOLD not empty....
{asm("nop;");};

*pSPORT1_TCR1 &= ~0x0001; // Disable Transmit INT

}//end DMA0_PPI_ISR

EX_INTERRUPT_HANDLER(SPORT1_ERROR_ISR) // <--|declaration in exception.h -->
{
 unsigned short statreg;
 statreg = *pSPORT1_STAT;

 if (statreg & TUVF){ //W1C
 *pSPORT1_STAT = statreg | TUVF;
 ssync();
 txUnderflowStatus++;
 ssync();
 }
 if (statreg & TOVF){ //W1C
 *pSPORT1_STAT = statreg | TOVF;
 ssync();
 txOverflowStatus++;
 ssync();
 }

 if (statreg & TXHRE){ //
 txHoldRegEmpty++;
 ssync();
 *pSPORT1_TCR1 &= TSPDISABLE; //tx disable
 ssync();
 }
 if (statreg & TXF){ //
 txFifoFull++;
 ssync();
 }

}//end SPORT1_ERROR_ISR

What SPI memories can be used for booting Blackfin processors?

analog@sgaur.hosted.jivesoftware.com — Wed, 08 Apr 2009 12:35:27 GMT

What 24-bit SPI memory devices can be used in SPI master boot on BF53x/ BF561 processors?

The Boot ROM code lists only a few ATMEL devices. Can we not use devices from other vendors?

SPI for AD1939 to BF532

analog@sgaur.hosted.jivesoftware.com — Fri, 31 Jul 2009 09:13:16 GMT

Hi all, I am new here and I have a problem with initialize audio codec AD1939 to BF532 DSP. I wrote init code in C, but by simulation SPI registers and DMA aren't set and I don't understand this. In simulator windows shows SPI registers ( for example: SPI_CTL [n/a]) - What mean this? Initialize for SPORT0 work good. Can you help me for finding my errors in code. I use for examples init code for codec AD1836 from BF533_EZ_KIT_LITE board. Thanks.

#include <ccblkfn.h>
#include <cdefBF532.h>
#include <defBF532.h>
#include <signal.h>
#include <stdio.h>

#define CODEC_1939_REGS_LENGTH 11

// SPI transfer mode
#define TIMOD_DMA_TX 0x0003

// SPORT0 word length
#define SLEN_32 0x001f

// DMA flow mode
#define FLOW_1 0x1000

int timer_count = 1;

// names for codec registers, used for iCodec 1939 TxRegs[]
#define PLL_Clock_Control0 0x0000
#define PLL_Clock_Control1 0x1000
#define DAC_CONTROL_0      0x2000
#define DAC_CONTROL_1      0x3000
#define DAC_CONTROL_2      0x4000
#define DAC_individual_mutes 0x5000
#define DAC_L1_VOLUME     0x6000
#define DAC_R1_VOLUME     0x7000
#define DAC_L2_VOLUME     0x8000
#define DAC_R2_VOLUME     0x9000
#define DAC_L3_VOLUME     0xA000
#define DAC_R3_VOLUME     0xB000
#define DAC_L4_VOLUME     0xC000
#define DAC_R4_VOLUME     0xD000
#define ADC_CONTROL_0     0xE000
#define ADC_CONTROL_1     0xF000
#define ADC_CONTROL_2     0x10000

volatile short sCodec1939TxRegs[CODEC_1939_REGS_LENGTH] =
{
         PLL_Clock_Control0 | 0x000,
         PLL_Clock_Control1 | 0x000,
      DAC_CONTROL_0   | 0x000,
               DAC_CONTROL_1   | 0x000,
               DAC_CONTROL_2   | 0x000,
               DAC_individual_mutes | 0x000,
               DAC_L1_VOLUME | 0x3ff,
               DAC_R1_VOLUME | 0x3ff,
               DAC_L2_VOLUME | 0x3ff,
               DAC_R2_VOLUME | 0x3ff,
               DAC_L3_VOLUME | 0x3ff,
               DAC_R3_VOLUME | 0x3ff,
               DAC_L4_VOLUME | 0x3ff,
               DAC_R4_VOLUME | 0x3ff,
               ADC_CONTROL_0   | 0x000,
               ADC_CONTROL_1   | 0x180,
               ADC_CONTROL_2   | 0x000
};

int tx_SPIbuffer[256];
int rx_SPIbuffer[256];

int Rx_buffer[256];
int Tx_buffer[256];

void init_SPORT0 (void)
{
//clear SPORT reg
*pSPORT0_TCR1 = 0;
*pSPORT0_TCR2 = 0;
*pSPORT0_RCR1 = 0;
*pSPORT0_RCR2 = 0;
// Sport0 receive configuration
// External CLK, External Frame sync, MSB first
// 32-bit data
*pSPORT0_RCR1 = RFSR;
*pSPORT0_RCR2 = SLEN_32;

*pSPORT0_TCR1 = TFSR;
*pSPORT0_TCR2 = SLEN_32;
// Enable MCM 8 transmit & receive channels
   *pSPORT0_MTCS0 = 0x000000FF;
   *pSPORT0_MRCS0 = 0x000000FF;

   // Set MCM configuration register and enable MCM mode
   *pSPORT0_MCMC1 = 0x0000; //reset MCMC1
   *pSPORT0_MCMC2 = 0x101c; //set MCMC2
}

void init_DMA (void)
{
//configure DMA for SPORT0 Rx
*pDMA1_PERIPHERAL_MAP = 0x1000;
// Configure DMA1
   // 32-bit transfers, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;

*pDMA1_START_ADDR = (void *)Rx_buffer [0] ;
   // DMA inner loop count
   *pDMA1_X_COUNT = 8;
   // Inner loop address increment
   *pDMA1_X_MODIFY = 4;

//configure DMA for SPORT0 Tx
   *pDMA2_PERIPHERAL_MAP = 0x2000;

   // Configure DMA2
   // 32-bit transfers, Autobuffer mode
   *pDMA2_CONFIG = WDSIZE_32| FLOW_1;
   // Start address of data buffer
   *pDMA2_START_ADDR = (void *)Tx_buffer [0];
   // DMA inner loop count
   *pDMA2_X_COUNT = 8;
   // Inner loop address increment
   *pDMA2_X_MODIFY   = 4;
}

void enable_DMA_sport0 (void)
{
// enable DMAs
   *pDMA2_CONFIG   = (*pDMA2_CONFIG | DMAEN);
   *pDMA1_CONFIG   = (*pDMA1_CONFIG | DMAEN);

   // enable Sport0 TX and RX
   *pSPORT0_TCR1 = (*pSPORT0_TCR1 | TSPEN);
   *pSPORT0_RCR1 = (*pSPORT0_RCR1 | RSPEN);
}
/*

*/

void init_SPI(void)
{
//Init SPI MASTER TX DMA
*pSPI_CTL = 0;
*pSPI_FLG = 0;

/* Set BAUD rate */
*pSPI_BAUD = 16;

/*use PF3 as spi device select */
*pSPI_FLG = FLS3; //ADC_LATCH

*pSPI_CTL =   SPE |       /* Enable SPI port */
    MSTR |       /* Master mode (internal SPICLK) */
    CPOL |       /* Active low SCK */
    SIZE |       /* 16-bit words */
               SZ |       /* Send zero or last word when SPI_TDBR is empty*/
            TIMOD_DMA_TX;      /* Start transfer with DMA read
        of SPI_RDBR, request further
        DMA reads as long as SPI DMA FIFO is not full*/

// Configure DMA5
   // 24-bit transfers
   *pDMA5_CONFIG = WDSIZE_32;
   // Start address of data buffer
   *pDMA5_START_ADDR = (void *)sCodec1939TxRegs;
   // DMA inner loop count
   *pDMA5_X_COUNT = CODEC_1939_REGS_LENGTH;
   // Inner loop address increment
   *pDMA5_X_MODIFY = 2;

// Map DMA5 to SPI
   *pDMA5_PERIPHERAL_MAP   = 0x5000;

/*Set up DMA5 to transmit*/
*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);      /* begin DMA */
}

void wait_SPI (void)
{
   unsigned int j;
   j = *pSPI_STAT;

   while (j & 0x0001 != 0x0001)
    j = *pSPI_STAT;
}

void Init_Sport_Interrupts(void)
{
   // Set Sport0 RX (DMA1) interrupt priority to 2 = IVG9
   *pSIC_IAR0 = 0xffffffff;
   *pSIC_IAR1 = 0xffffff2f;
   *pSIC_IAR2 = 0xffffffff;

    // enable Sport0 RX interrupt
   *pSIC_IMASK = 0x00000200;
   ssync();
}

void main (void)
{
int b;
init_DMA ();

init_SPI ();
wait_SPI ();
enable_DMA_sport0 ();
init_SPORT0 ();
Init_Sport_Interrupts ();
while (1)
{
b++;
}
}

Yanko Todorov.

EBIU controller configuration with ARDY enabled

analog@sgaur.hosted.jivesoftware.com — Mon, 13 Jul 2009 07:46:02 GMT

We are testing WLAN module on our BF561 platform with EBIU interface. We are using AMS2 space for WLAN module with ARDY enabled (EBIU_AMCTL1=0x99C222C3). We are observing that AMS2 bank configuration value for access time of 2 cycles is not taking effect and we are always seeing 15 cycles for each Rd/Wr access though ARDY has gone high much before. We tried varying the access cycles from 2 to 9 and we always see
15 cycles of access time.

I am attaching waveform capture for the case where we changed timing settings to EBIU_AMBCTL1=0x99C222C3. Attached waveform is for read transaction and seen the access time is always 15 cycles (100MHz SCLK/10ns period). A,B,C,D,E cursors have been placed at different events which are self explanatory.

BF518 EZ Board - Orcad files

analog@sgaur.hosted.jivesoftware.com — Wed, 05 Aug 2009 14:12:13 GMT

This thread would be better placed in the VisualDSP++ Tools category, and has been moved here: BF518 EZ Board - Orcad files

Thank you.

How do I begin doing an Audio Application on Blackfin?

analog@sgaur.hosted.jivesoftware.com — Wed, 08 Apr 2009 12:30:56 GMT

I am a beginner and am interested in using the Blackfin processor for some audio processing applications. Can you guide me through right from what I should buy, and if there is an A/D converter on board? Should I buy an extender board also?

SHARC SPI slave select and IRQ/FLAG pins

analog@sgaur.hosted.jivesoftware.com — Mon, 26 Jan 2009 14:34:17 GMT

Can you please elaborate on the operation of the IRQ/FLAG pins on the ADSP-2126x and ADSP-21362/3/4/5/6 processors, in conjunction with their use as SPI slave select outputs as well?

change BF533 core timer TPERIOD value on the fly

analog@sgaur.hosted.jivesoftware.com — Tue, 25 Aug 2009 01:17:02 GMT

In my BF533 board, I used core timer to generate the system time slot, which may change, according to various conditions. The system time slot needs to be continuous, so I need to change the core timer TPERIOD value on the fly. But I found that the TCOUNT will be set to the same value as long as I set TPERIOD. I want to keep TCOUNT value, while to change the TPERIOD to different value, so that the system time slot could change in the next period.

I checked BF533 hardware mannual, and found that TCOUNT will keep the same value with TPERIOD if TPERIOD is changed. Is there any workaround?

I also found that in VDSP simulator environment, TCOUNT kept its old value if TPERIOD is changed, which is different from emulator environment (TCOUNT will keep the same value with TPERIOD if TPERIOD is changed).

BF561-Multiple DXE boot based on BF Timer Interrupt

analog@sgaur.hosted.jivesoftware.com — Fri, 19 Jun 2009 05:18:16 GMT

Hi All,

Based on EE272 notes for Mutliple DXE booting, I havedownloaded the accompanied example code

and did the following changes to suite our custom BF561 based board.

In blink_lower -- Changed main.c to blink the LED of our Custom board ( glows LED 1 & 3)

blink_upper -- Changed main.c to blink the LED of our Custom board ( glows LED 2 & 4)

In cmds.c -- Used Timer interrupt of blackfin( instead of PF/SW given in the example code)

Initialized timer routine and registered timer interrupt,On every timer interrupt,

the DXE1 and DXE2 should be booted alternatively

Then I have generated the multiple.ldr file and flashed my custom board.

On poweron I have noticed only DXE1 is executed continuously( LED 1& 3 is glowing)

Switching to DXE2 is not happening on the next timer interrupt..

I have attached the code with this.Can you help me to find out why the

switching of DXE's is not happening when timer interrupt occurs ?

Thanks in advance.

BF527 sample code to hibernate USB

analog@sgaur.hosted.jivesoftware.com — Tue, 23 Jun 2009 13:51:05 GMT

I've got a BF527 project that has a USB charger detection chip (STUSBCD01B: http://www.stm.com/stonline/products/literature/ds/15172.pdf) to determine if my device is connected to a host USB port, or a high-power USB wall charger. The detection chip works fine if the rest of my hardware is powered off, but if the BF527 is running, its USB PHY interferes with the D+/D- sensing used by the detection chip.

What I'd like to do is have the BF527 normally run with the PHY hibernated, so D+ and D- are tristated. If a user connects the device to a wall charger or USB port, VBUS goes high. The charge detection chip determines which source is connected within 200ms, so I'd like to have the BF527 sense VBUS appearing, wait at least 200ms (to give the detection chip time to work), and then take the USB PHY out of hibernation so it can operate normally. When the USB input is unplugged, VBUS will go back to zero, and the BF527 would hiberate the PHY driver again.

It looks like bits CS_HBR and CSR_RSTD in USB_APHY_CNTRL2 can do this. Is there any documentation on how using these can interact with the rest of the BF527 USB system. Can I simply hibernate and unhibernate the PHY driver at will, without interferring with the ADI USB driver stack, or do I need to teardown/restart the entire USB subsystem each time? Can VBUS still be sensed when the PHY is in hibernate?

Is there any sample code that shows any use of those bits?

Reading level from edge sensitive interrupts

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Apr 2009 11:58:48 GMT

In BF533, I want to have the PF set for edge sensitive interrupt, at the same time I want to read the level. How is it possible?

SRAM vs. SDRAM?

analog@sgaur.hosted.jivesoftware.com — Wed, 08 Apr 2009 12:28:14 GMT

SRAM and SDRAM compared, how many SCLK cycles are needed for one 16-bit memory transfer when executing directly from that memory with Cache OFF?

About Blackfin SPI Boot

analog@sgaur.hosted.jivesoftware.com — Wed, 12 Aug 2009 04:51:31 GMT

Hi,

Could Blackfin CPU support 32 bits address SPI flash ?

Currently the CPU we used is bf536, the datasheet says it can support boot from 24 bits address SPI flash. That means that it could only boot from Flash which its size less than 2^24=128M bits=16 MB.

Currently, we want to use a 256Mb=32MB SPI flash, Can bf536 boot from it? Which Blackfin CPU support it?

How many cycles to complete a system soft reset?

analog@sgaur.hosted.jivesoftware.com — Wed, 15 Apr 2009 11:38:47 GMT

What is the approximate time or cycles it takes to reset the peripherals? That is, to complete a system soft reset?

Need a example code with BF-533 Ez-Kit Lite and Audio Extender

analog@sgaur.hosted.jivesoftware.com — Fri, 19 Jun 2009 06:46:38 GMT

hi,

i want to know the jumper and switch settings for ez-kit lite when we are using audio extender card BF-533 ez-kit lite. If any example code available that helps us lot.

with regrads,

sunil

How do I debug my application which is not booting properly

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Apr 2009 08:52:34 GMT

Hi,

My application code works fine while running from emulator, but it fails when booted from the flash. How do I debug it.

How many PC’s can I use my license number on?

analog@sgaur.hosted.jivesoftware.com — Wed, 18 Feb 2009 10:12:21 GMT

How many PC’s can I use my license number on?

Number of cycles taken by different instructions to copy a buffer is different.

analog@sgaur.hosted.jivesoftware.com — Wed, 08 Apr 2009 12:25:19 GMT

When I use different instructions to copy a buffer from one location in memory to another, I observe that the number of cycles taken is different. The instructions are:

memcpy
for loop
loop in assembly.

I also observe that a memset instruction when used before starting cycle count has an effect on the count. Why?

Digital Filter Design tool for Blackfin

analog@sgaur.hosted.jivesoftware.com — Fri, 31 Jul 2009 14:14:46 GMT

Hello to everybody!

This is my first post in this forum.

I've been using Blackfin for a couple of years (and I developed some project with ADSP-218x before) but I've never been able to find a nice Digital Filter Design tool that gives filter coefficients in the format required by Blackfin DSPs.

Usually I use fract16 data type, and most of the Digital Filter Design tools I tried don't provide an option to consider quantization...

I think that the old FilterExpress from Systolix is very, very good to design FIR filters.

For IIR ones, it doesn't give coefficients in two vectors a[] and b[] as the Blackfin expects, but only as a bi-quad cascade.

Does Analog Device supply a free tool for this purpose?

Best regards

vix

adau1445 serial output data width issue

analog@sgaur.hosted.jivesoftware.com — Wed, 09 Sep 2009 08:24:47 GMT

I have set adau1445 serial output line to TDM2 16bit 48Khz slave mode, and inside DSP, I'm using a Tone (Lookup/sine) block to generate 2Khz sine wave to the serial output line. From what I've probed, the serial output data is always 24 bits, i.e. the lower bits not set to 0s. According to the datasheet(rev. A), "The output stream always has space for 24 bits of data, but if the word length is set lower, the extra bits are set as 0s.", aparently it's not what I'm seeing. Do you guys know why? Thanks.

Is it possible to initialize memory from a binary file?

analog@sgaur.hosted.jivesoftware.com — Thu, 24 Sep 2009 01:15:55 GMT

I would like to initialize a block of memory with the contents of a binary file (on a Blackfin processor, if you are interested). Is there a C/C++ #pragma in the compiler, or an assembler directive to do this?

Thanks.

--wpd

Debugging Flash-based code

analog@sgaur.hosted.jivesoftware.com — Tue, 13 Oct 2009 20:59:50 GMT

The saga continues. I have successfully edited the Flash Programmer driver dxe and can now program to the Flash. In addition, I have made the relevant changes to the boot loader file to match my hardware (I think). For discussion sake, my code generates three signals. They are based of the Timers, via interrupts. When I run from the emulator, I get all three signals. When I program the "exact" same code into Flash, I only get one of the signals. I know that I have done something incorrectly, but how do I figure out what is wrong?

My question is: Is there a way to step through the code that was copied from Flash to SDRAM for execution? I have used other IDEs where there was "target mode" that could see the assembler code, and could step through it.

I am using VDSP 5.0.6 with three 21368s.

Thanks

USBIO in VDK

analog@sgaur.hosted.jivesoftware.com — Fri, 24 Jul 2009 13:28:58 GMT

Hi,

We have integrated USBIO file io code available in Analog devices folder into VDK kernel. We are testing this code on BF527 EZKit Lite and VDSP5.0 with update 6.

In the kernel we have one boot thraed and two parallel running threads with file io. The two threads are having same priority. Round robin schelduling has been used. In this case, part of file transfer has been successful. Later no data tansfer taken file. After halting, the pointer is at while(g_bRxflag == 0), in usb_read function, i.e the system waiting USB to be configured. In the VDK history window, one thread shows that it has been blocked by mutex. Can anybody guess what is making the problem in this situation.

thanks

ananth

Detection of USB Lan Extender

analog@sgaur.hosted.jivesoftware.com — Thu, 18 Jun 2009 08:26:36 GMT

hi,

When i tried to connect the USB LAN Extender along with the BF561 EZ-kit Lite,it shows that "the USB LAN that is connected is malfunctioning and windows cannot recognise the device.Is there any way to check why it is not getting connected?.

Details regarding the Platform:

VDSP++ 5.0, Update 4

USB LAN Extender rev 2.1.

Thanks and regards,

Geetha.M

dma error caused by writing flash

analog@sgaur.hosted.jivesoftware.com — Thu, 24 Sep 2009 03:10:33 GMT

Hello ,everyone. I am developping a program on bf561which use both PPI0 and PPI1. DMA error happened everytime when writing to intel flash. I have checked that wring flash only cost 50 us . So why this happened? Does anyone has gotted same problem?

STOPCK bit

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Apr 2009 12:03:31 GMT

Is STOPCK bit is cleared in the transition from Sleep to Active/Full On?

Maximum speed of operation for SPI on SHARC Processors

analog@sgaur.hosted.jivesoftware.com — Mon, 13 Apr 2009 00:40:34 GMT

What is the maximum speed of operation for SPI on SHARC Processors?

Ethernet connection from PC to ADSP-BF537 EZ Kit Lite

analog@sgaur.hosted.jivesoftware.com — Thu, 01 Oct 2009 19:46:11 GMT

Hello,

is it normal that my laptop doesn't even recognize that a network cable (crossover) is connected to it if I plug into my board and then connect it to my laptop? I also tried to connecting the board to my router and it didn't even show up in the connected devices list (not to mention it didn't get an IP)? I was wondering whether there is something I am neglecting or whether the ethernet on my ADSP-BF537 board is faulty.

thanks,

Developing Sigma DSP Cluster

analog@sgaur.hosted.jivesoftware.com — Mon, 29 Jun 2009 03:35:40 GMT

Hi sirs

First, I 'm searching for people that uses the Sigma DSP (I trying to use AD1940).

My first project is to develop a AD1940 cluster to perform and audio routing system (with some improved features).

The basic project concept is :

http://jeanfernandes.com/files/images/dspsigmaex.pdf

The idea is to put all of them on same board.

Some questions:

a) Is it possible to wire the Audio Input Codec (as master) on 6 DSP without glue logic ?

b) And about the Master Clock ? Usually I use a hibrid square wave clock up to 3 chips. What glue logic is really necessary to

this project ?

c) Is it possible to draw the board just using 2 layers ?

d) I need to put audio compressor on all inputs and I saw that the curve has 32 points, but I dont know how to map an HMI user interface

to control all points of this block. My boss suggest me annotate several curves and list them to user choose (its a simple manner but ....)

e) If I use the TDM channel (to simplify design) what the maximum sampling rate (I suppose that is 48 Khz).

f) I will develop the controller firmware using C (ARM7). Does anyone has an SDK to control the IC's 1940 and 1939 (using SPI) ?

Regards

Jean Fernandes

Using Eval Mini AD1940 Evb to test.

How do Reset, Reload and Restart differ?

analog@sgaur.hosted.jivesoftware.com — Fri, 06 Feb 2009 16:16:04 GMT

How do Reset, Reload and Restart differ?

Ilatch bit

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Apr 2009 12:06:48 GMT

ILATCH bit of an interrupt is usually set when an unmasked interrupt is triggered from the system or by issuing a RAISE X instruction. However, this doesn’t happen when the interrupt is re-triggered at system level, which is already being serviced. Why is that?

Changed email address but replies still sent to old one.

analog@sgaur.hosted.jivesoftware.com — Wed, 05 Aug 2009 20:34:18 GMT

I've changed my email address since joining the group and opening a discussion (Fast Lookup table) but messages posted to that discussion continue to be sent to my old address. How do I fix that?

Thanks and best regards,

Dave

HPUSB ICE Load error

analog@sgaur.hosted.jivesoftware.com — Thu, 08 Oct 2009 07:36:27 GMT

Hi ,

I am using HPUSB ICE .

When i build and download the program i get the following message .

The target has requested to disconnect from the IDDE.
Reason: GetReg failed
Do you want it to disconnect?

But if a build the same project and put it on Flash Boot it works fine .

ICE was working fine with the same project earlier . we tried it with a Diffrent ICE and i get the same mess .

Could you please let me know with regards to this .

Thanking you

With regards

driver for flash programmer

analog@sgaur.hosted.jivesoftware.com — Thu, 01 Oct 2009 14:59:44 GMT

Hi all

in the visual DSP library they have driver for flash memory with boot sectors at the end of the flash.

Anyone knows where i can get driver for flashs with boot sectors at start of the flash memory (sector 0 : 0x0000-0x4000,sector 1-3: 0x4000-0x6000,0x6000-0x8000,0x8000-0x10000)?

Thanks

Spread Spectrum oscillators

analog@sgaur.hosted.jivesoftware.com — Tue, 31 Mar 2009 13:53:45 GMT

Can I use Spread Spectrum Oscillators for my Blackfin DSP's?

Divfract32 Lib function

analog@sgaur.hosted.jivesoftware.com — Tue, 29 Sep 2009 12:33:41 GMT

Hi Analog Devices,

The divfract32 from Analog Devices library gives 1.31/1.31==>1.31 result.

But the precondition makes me a bit unhappy. "the numerator is always less than the denominator" I can understand this.

But how to circumvent this problem? Also is it possible to take inverse of a 1.31 number and multiply?

how would the inverse look like? 1/1.31 is not allowed in fractional math or?

Please let me know more about it. Is there any application note on this topic?

Regards

Dspgeek

fwrite/ fputc error

analog@sgaur.hosted.jivesoftware.com — Thu, 02 Jul 2009 06:05:03 GMT

I am using BF537 ez kit lite.

I am implementing its example .............\Analog Devices\VisualDSP 5.0\Blackfin\Examples\ADSP-BF537 EZ-Kit Lite\Getting Started Examples\Part_2_1.

Simply i have defined a File pointer in it and read a file and store it in a dynamically created chracter array. Its ok.

The problem is when i save this file to the disk using fwrite, it writes the file but after some interval 4 bytes are re copied as shown in figure attached. Why these bytes are re-copied. If you save it at once or in chunks same problem occours.

I have checked the data of array its ok but i dont no why its is not writing the whole array truely into the file.

Figure:-

Two files are compared (actual file and saved file) which are in background.

Result of comparasion is in the file which is on forefront.

Can someone explain the use of the fir_interp_fr16() function

analog@sgaur.hosted.jivesoftware.com — Wed, 09 Sep 2009 10:14:54 GMT

I want to upsample an 8kHz signal to 48kHz, i.e. interpolate by a factor of 6. (this is on BF52x processor)

fir_interp_fr16() function seems to do what I need, but I have a problem getting this function to work. Specifically I cannot find any explanation of the exact order of the coefficients required by this function.

I already have a set of coefficients for a low pass filter (4kHz cut off) which I have used successfully in the fir_decima_fr16() function. (to go from 48kHz to 8kHz)

If these are in the order :

c0, c1, c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20, c21, c22, c23, c24

What then is the order of these co-efficients that I must present to the fir_interp_fr16() function ?

Thanks.

DMA into cached SDRAM

analog@sgaur.hosted.jivesoftware.com — Wed, 08 Apr 2009 11:41:02 GMT

Would there be a problem if a peripheral does DMA into SDRAM memory for which cache is enabled?

What is the maximum DDR size that BF54x can support?

analog@sgaur.hosted.jivesoftware.com — Wed, 21 Jan 2009 16:32:41 GMT

Hi,

Is there an manual/data sheet error of the size of DDR that BF54x can be
supported?

From BF54x HRM,

* Supports industry standard double data rate (DDR SDRAM) from 64 Mbit to
512 Mbit device sizes with a configuration of x4, x8, or x16.
* Provides 16-bit wide data interface to DDR SDRAM.
* Supports up to 256 MB of DDR SDRAM with one external bank.

The manual said BF54x can support up to 256MB per external bank, however,
there is another paragraph saying that it can support up to 512Mb device which
is only 64 MB. This description is confusing. Can we connect a 1 Gbit or
larger DDR? If not, how can we get 256MB per external bank.

Kaushal

SPI Slave booting using software solution

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Jul 2009 23:06:02 GMT

Hi,

I am using the SPI slave booting for bootloading the ADSP21369 using a microcontroller, where the ADSP21369 is the slave and microcontroller is a master. I am using the Software solution given in EE-177 (SHARC SPI slave booting). The SPI baud rate is 625 KHz

I am using the software solution based on EE-177 to pause the bootloading when the ADSP21369 is initialising the zero-init sections.

Can anyone please answer my questions below:

1) Is the FINAL_INIT section the last section? Can there be any other sections after the Final init.

2) How do we find the word count of the FINAL_INIT section.

3) If I am using single processor, will there be a MULTI_PROC section?

4) Should we initialise the core speed and SDRAM in the kernel or in the application code? What difference does it make?

Thanks very much.

Regards,

A-weighting / C-weighting filter

analog@sgaur.hosted.jivesoftware.com — Fri, 21 Aug 2009 07:07:20 GMT

Hello,

I am thinking about implementing an A-weighting and an C-weighting filter into a ADAU1701. In a previous version of a project I implemented these filters in the analog domain. For the next revision I am planing to transfer them to the digital domain. The response will be more accurate and not sensitive for component tolerances.

What do you thing is the best way to implement? Combining various Filters or using FIR or IIR. Maybe anyone out there has done this before and likes to share his experiences. Or is this for some reasons not a good idea to do this.

Thanks for sharing your thoughts

Regards

Bernd

SDRCON and SYSREG values do not update as expected

analog@sgaur.hosted.jivesoftware.com — Fri, 08 May 2009 14:00:02 GMT

When I run my application, I cannot change the value of the the SYSREG and SDRCON registers. If I step through the code, though, I notice my settings are correctly applied. What is the reason for this behaviour?

code examples for benchmarking

analog@sgaur.hosted.jivesoftware.com — Tue, 13 Oct 2009 12:07:44 GMT

Hi,

I'm evaluating the ADSP-21469 for the use in professional audio amplifiers.I found this site with benchmarks on the analog hompage:

http://www.analog.com/en/embedded-processing-dsp/sharc/adsp-21469/products/benchmarks/sharc_benchmarks/resources/fca.html

Do somebody have any code examples for benchmarking, so I can do these benchmarks on my own?

Thanks,

Marc

Form entry -- question answered

analog@sgaur.hosted.jivesoftware.com — Tue, 21 Jul 2009 10:20:15 GMT

You post a question

You get a reply

The reply is the best thing since sliced bread

You click -- mark as answered -- in the form

Later you find that it was not the answer -- how do you unclick the "the answer" option so you can restart the thread and get other replies?

cache

analog@sgaur.hosted.jivesoftware.com — Thu, 25 Jun 2009 05:56:58 GMT

Dear All,

I m new to this. How can i visualize the cache working?

is this can be done in VDSP simulator?

thanks and regards,

Maximum CLKIN frequency for SHARC Processors

analog@sgaur.hosted.jivesoftware.com — Mon, 20 Apr 2009 15:31:20 GMT

1. What is the maximum crystal frequency that can be used with the internal SHARC oscillator circuit? The datasheet specifies a tck min of 18 ns (55 MHz) but is that specification for an external oscillator, a crystal or both?

ADSP21364 - SRU

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Jul 2009 19:48:23 GMT

Hi,

I am using SPIB on ADSP21364 but having problems with connecting the SPIB signals to DAI pins. The SPI is in master mode and the CCLK is output and i connected it on DAI pin 10. Does it have to be this pin configured as an output?For example:

SRU (HIGH, PBEN10_I);
SRU (SPIB_CLK_O, DAI_PB10_I);

Is that true? And how can i chek if this signal is realy conecting to DAI pin 10?

I allso did that:

SRU (HIGH, PBEN11_I);

SRU (SPIB_MOSI_O, DAI_PB11_I);

SRU (LOW, PBEN12_I);
SRU (DAI_PB12_O, SPIB_MISO_I);

Is it true tha too?

21369 SDRAM problem, two 16-bit devices arranged as a single 32-bit

analog@sgaur.hosted.jivesoftware.com — Wed, 16 Sep 2009 13:38:10 GMT

Hello,

I am experiencing an odd problem with my SDRAM. I have a single 21369 processor attached to two Micron MT48LC16M16 16-bits SDRAM chips. The chips are arranged to function as a single 32-bit device. They are attached via MS1. It appears as though I have some functionality of the memory, but its behavior is a bit bizarre. Every four addresses seem fine, the next four do not, then repeat. For example if I do a mem fill from VDSP of twenty addresses starting at XXXX00 with data 1234ABCD I would get something like:

XXXX00 : 1234ABCD

XXXX01 : 1234ABCD

XXXX02 : 1234ABCD

XXXX03 : 1234ABCD

XXXX04 : 00000000

XXXX05 : 00000000

XXXX06 : 00000000

XXXX07 : 00000000

XXXX08 : 1234ABCD

XXXX09 : 1234ABCD

XXXX0A : 1234ABCD

XXXX0B : 1234ABCD

XXXX0C : 00000000

XXXX0D : 00000000

XXXX0E : 00000000

XXXX0F : 00000000

XXXX10 : 1234ABCD

XXXX11 : 1234ABCD

XXXX12 : 1234ABCD

XXXX13 : 1234ABCD

I can provide details on pin connections and setup code if need be. Just thought I'd throw this out there first.

Glen

delay counts..

analog@sgaur.hosted.jivesoftware.com — Wed, 01 Jul 2009 09:59:08 GMT

Hi,

I am using BF561. I need to give 1 second delay. How do i accomplish.

Say, if is use something like this

for ( i=0;i<count;i++);

How do i compute count value?.

BF EZ-LITE kit and VISUAL DSP

analog@sgaur.hosted.jivesoftware.com — Thu, 01 Oct 2009 13:12:13 GMT

This thread would be better placed in the VisualDSP++ Development Tools category, and has been moved here: BF EZ-LITE kit and VISUAL DSP

Thank you.

How can I use BF518's 1588 feature to synchronize LED's in a distributed system?

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Apr 2009 20:42:44 GMT

Hi,

I have a distributed system, which includes a bunch of units based on BF518 interconnected with Ethernet. Each unit has some LED's to control. How can I synchronize the LED's of all the units?

What does the X in the processor part number mean?

analog@sgaur.hosted.jivesoftware.com — Mon, 26 Jan 2009 15:48:15 GMT

There is an X in the part number on my DSP. What does this mean?

TigerSHARC simulator accuracy

analog@sgaur.hosted.jivesoftware.com — Sun, 20 Sep 2009 21:55:57 GMT

Am running a simple rectify program on TigerSHARC TS201S

// C++ code
int *HalfWaveRectifyReleaseMode(int initial_array[], int final_array[], int N) {
 int *return_pt = final_array;

 if (N <= 0) return NULL;

 for (int count = 0; count < N; count++) {
 if (initial_array[count] > 0)
 final_array[count] = initial_array[count];
 else final_array[count] = 0;
 }
 return return_pt;
}

Using the code to demonstrate differences in speed with various modes of programming -- debug C, release C and custom assembly code -- float and int versions of rectify

We then go in and try to identify areas where stalls might occur to understand the behaviour of the architecture

Board is ADDS-TS201S-Exlite Rev 1.1 -- back of board says 1-D-1.2

There is nearly a factor of two between timings using cycle counter on the board and those provided with the simulator -- any idea why?

Consistent behaviour across all forms of program (C, debug, relase, asm)

Since I am counting cycles then "board speed" does not count -- meaning cycles / us (power save mode) is irrelevant, and I did not think that TigerSHARCs had a power save mode anyway

Board results

uS / point Integer Debug C 0.152225, Release C 0.022700, First ASM 0.016825
    uS / point Float Debug C 0.157625, Release C 0.047850, First ASM 0.017125
    us -- averageTime 0.003194, precision (maxTime - minTime) / 2 0.000088, acceptable 0.000512
    Succesful link to test file CodeTimingComparison_Test_cpp.
    Cycles / point Integer Debug C 75, Release C 11, First ASM 8
    Total cycles Integer Debug C 12044, Release C 1816, First ASM 1358
    Cycles / point Float Debug C 77, Release C 23, First ASM 8
    Total Cycles Float Debug C 12474, Release C 3828, First ASM 1352
    Cycles averageTime 0, precision (maxTime - minTime) / 2 0, acceptable 5
    Succesful link to test file CycleCounter_CodeTimingComparison_Test_cpp.
    Succesful link to test file ExploreTigerSHARCASM_Test_cpp.
    Succesful link to test file Rectify_cpp.
    Success: 17 blackbox tests passed.
    Blackbox Assert statistics: 0 Failures, 0 Expected Failures, 28 Successes.
    Whitebox Assert statistics: 0 Failures, 0 Expected Failures, 0 Successes. (Includes C Test statistics)
    Test time: 0.00104717 seconds.

Simulator results

uS / point Integer Debug C 0.072787, Release C 0.010525, First ASM 0.010450
    uS / point Float Debug C 0.086925, Release C 0.031625, First ASM 0.010525
    us -- averageTime 0.001835, precision (maxTime - minTime) / 2 0.000044, acceptable 0.000512
    Succesful link to test file CodeTimingComparison_Test_cpp.
    Cycles / point Integer Debug C 36, Release C 5, First ASM 5
    Total cycles Integer Debug C 5791, Release C 826, First ASM 831
    .\CycleCounterCodeTimingComparison_Test.cpp(64): Error: Failure in CycleCounter_CodeTimingComparison_Int: integerRelease > firstIntegerAssembly
    Cycles / point Float Debug C 43, Release C 15, First ASM 5
    Total Cycles Float Debug C 6945, Release C 2531, First ASM 838
    Cycles averageTime 0, precision (maxTime - minTime) / 2 0, acceptable 5
    Succesful link to test file CycleCounter_CodeTimingComparison_Test_cpp.
    Succesful link to test file ExploreTigerSHARCASM_Test_cpp.
    Succesful link to test file Rectify_cpp.
    FAILURE: 1 out of 17 blackbox tests failed.
    Blackbox Assert statistics: 1 Failures, 0 Expected Failures, 27 Successes.
    Whitebox Assert statistics: 0 Failures, 0 Expected Failures, 0 Successes. (Includes C Test statistics)
    Test time: 0.00064387 seconds.

In case I am doing something obviously wrong -- Example tests looks like this.

This is a TigerSHARC variant of the UnitTest++ testing framework found at SoureForge

#define NUMPOINTS 160

TEST(CycleCounter_CodeTimingComparison_Int)
{

    int initialArray[NUMPOINTS] = {
                    1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,
                    1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,
                    1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,
                    1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,
                    1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,
                    1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,
                    1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,
                    1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6,   1, 2, 3, -4, 6
    };
int finalArray[NUMPOINTS] = {0, 0, 0, 0, 0};

    __int64 measuredTimes[5];

    measuredTimes[0] = __ReadCycleCounter64( );
        HalfWaveRectifyDebugMode(initialArray, finalArray, NUMPOINTS);
    measuredTimes[1] = __ReadCycleCounter64( );
        HalfWaveRectifyReleaseMode(initialArray, finalArray, NUMPOINTS);
    measuredTimes[2] = __ReadCycleCounter64( );
        HalfWaveRectifyASM_Int(initialArray, finalArray, NUMPOINTS);
    measuredTimes[3] = __ReadCycleCounter64( );
    measuredTimes[4] = __ReadCycleCounter64( );

    __int64 timerOverHead = (measuredTimes[4] - measuredTimes[3]);
    __int64 integerDebug =         (measuredTimes[1] - measuredTimes[0] - timerOverHead) / NUMPOINTS;
    __int64 integerRelease =     (measuredTimes[2] - measuredTimes[1] - timerOverHead) / NUMPOINTS;
    __int64 firstIntegerAssembly =
                                 (measuredTimes[3] - measuredTimes[2] - timerOverHead) / NUMPOINTS;
    printf("Cycles / point Integer Debug C %d, Release C %d, First ASM %d\n",
        (int) integerDebug, (int) integerRelease, (int) firstIntegerAssembly);

    timerOverHead = (measuredTimes[4] - measuredTimes[3]);
    integerDebug =         (measuredTimes[1] - measuredTimes[0] - timerOverHead);
    integerRelease =     (measuredTimes[2] - measuredTimes[1] - timerOverHead);
    firstIntegerAssembly = (measuredTimes[3] - measuredTimes[2] - timerOverHead);
    printf("Total cycles Integer Debug C %d, Release C %d, First ASM %d\n",
        (int) integerDebug, (int) integerRelease, (int) firstIntegerAssembly);

    CHECK( integerDebug > integerRelease);                   // RELEASE FASTER
    CHECK( integerDebug > firstIntegerAssembly);   // OUR ASM FASTER
    CHECK( integerRelease > firstIntegerAssembly); // OUR ASM FASTER
}

Thanks

Mike

Problem about ee323 using VDSP5.0

analog@sgaur.hosted.jivesoftware.com — Sun, 19 Jul 2009 06:27:17 GMT

While executing post-build command ($(VDSP)/elf2flt Debug/Example_1_-_DLM.dxe), an error occured in msvcr80.dll and it failed to generate Example_1_-_DLM.dxe.bflt.

If I use VDSP4.5, post-build command will succeed.

Is there other software I should install ,like .net framework x.x etc?

Instruction execution after deep sleep mode.

analog@sgaur.hosted.jivesoftware.com — Tue, 11 Aug 2009 10:22:49 GMT

Hello!

My question is, how can occur that, if I place the BF538 to deep sleep mode with the PDWN bit in the PLL_CTL register, then it executes instruction that occur after placing to deep sleep mode instruction.

Maybe I'm wrong, but first of all I wait that, after this setting It won't execute any instruction until a RTC/Hw Reset irq, because of halting system/core clock. So if i send it to deep sleep with this bit setting, and the next inctruction to toggle this bit back it wakes up, it's not the way it's good I think

Thanks in advance.

MJPEG solution ?

analog@sgaur.hosted.jivesoftware.com — Tue, 13 Oct 2009 08:33:20 GMT

This thread would be better placed in the Software Modules, Starter Kits and Software Development Kits category, and has been moved here:MJPEG solution ?

thank you.

Filter or source frequency measurement does not match that of SigmaStudio

analog@sgaur.hosted.jivesoftware.com — Thu, 23 Jul 2009 19:44:58 GMT

My tone generator or filter in SigmaStudio is set with a certain center frequency, but when I measure it on the hardware, it differs. What is going on?

VSync callback with PPI in Input Mode

analog@sgaur.hosted.jivesoftware.com — Wed, 07 Oct 2009 08:59:38 GMT

ADI-Support,

I would like to synchronize my captured video with the external VSync. from a CMOS Sensor connected to the PPI0. Is there a way to detect the VSync e.g. by an interrupt or callback routine. In this case PPI0 is used and the Pin would be PPI0SYNC2 which is ADI_TMR_GP_TIMER_9.

Which is the best solution to to this.

Regards

Thomas

SDH: How to read small block from the FIFO?

analog@sgaur.hosted.jivesoftware.com — Sat, 18 Jul 2009 09:47:31 GMT

Hi,

1. How to read a small block from Receive FIFO in Secure Digital Host (SDH) interface of ADSP-BF547?

Due to Simplified Version of PHYSICAL LAYER SPEC on SD Card the size of SCR Register is 64 bits (See Sectin 5-6, page 89).

How to read SCR Register (8 bytes) from Receive FIFO using block mode transfer? It seems impossible to read it neither by DMA nor by core.

2. It seems there is an error in Hardware Reference (Volume 2 of 2) Preliminary, Revision 0.4, August 2008 for ADSP-BF54x Blackfin Processor.

page 23-22. Figure 23-6. SDH Power Control Register (SDH_PWR_CTL):

as shown in Figure 23-6:

Power On (PWR_ON) - 00 - Power on

in reality to enable power it must be:

Power On (PWR_ON) - 11 - Power on

Thanks.

About ADIS16355 SPI-OUT

analog@sgaur.hosted.jivesoftware.com — Mon, 31 Aug 2009 07:14:51 GMT

Hello,

I've bought ADIS-16355 and choose AT89C51ED2 to read this chip.

I would like to connect ADSP21369 with ADIS16350 by SPI.

Please help me, show me how it works.

My code like follow

/************************************************************/

void main(void)

{

uart_init();

spi_init();

timer2_start(DELAY_50MS);

while(1)

{

SPDAT=data_example; /* send an example data */

while(!transmit_completed);/* wait end of transmition */

transmit_completed = 0; /* clear software transfert flag */

SPDAT=0x00; /* data is send to generate SCK signal */

while(!transmit_completed);/* wait end of transmition */

transmit_completed = 0; /* clear software transfert flag */

data_save = serial_data; /* save receive data */

}

void spi_init(void)

{

SPCON |= 0x10; /* Master mode */

P1_1=1; /* enable master */

SPCON |= 0x82; /* Fclk Periph/128 */

SPCON &= ~0x08; /* CPOL=0; transmit mode example */

SPCON |= 0x04; /* CPHA=1; transmit mode example */

IEN1 |= 0x04; /* enable spi interrupt */

SPCON |= 0x40; /* run spi */

EA=1; /* enable interrupts */

}

void it_SPI(void) interrupt 9 /* interrupt address is 0x004B */

{

switch ( SPSTA ) /* read and clear spi status register */

{

case 0x80:

serial_data=SPDAT; /* read receive data */

transmit_completed=1;/* set software flag */

break;

defaule:

break;

}

/*****************************************************************************/

Plz give me some example code to access ADIS-16355.

Thanks

Anson

32-bit optimized FFTs for Blackfin?

analog@sgaur.hosted.jivesoftware.com — Mon, 06 Jul 2009 23:57:15 GMT

I need a 32-bit optimized FFT for Blackfin. C-callable is preferred. Radix 2, Radix 4, in place or out of place. The inputs should be 32-bit and the final answer too.

VisualDSP++ 3.5 Flash Programmer plugin error

analog@sgaur.hosted.jivesoftware.com — Tue, 16 Jun 2009 22:27:15 GMT

Hello,

I'm trying to program my external flash device with a Load File and I keep getting the following error...

Error Processing Command

Error verifying write to flash while executing command WRITE.

I don't think my load file image is bad because I'm able to use the ICE emulator with the DXE for debugging without a problem.

Thank you

My target is a ADSP-2187 processor.